Transient Fault Tolerance via Dynamic Process-Level .ppt

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1、Transient Fault Tolerance via Dynamic Process-Level Redundancy,Alex Shye, Vijay Janapa Reddi, Tipp Moseley and Daniel A. ConnorsUniversity of Colorado at Boulder Department of Electrical and Computer Engineering DRACO Architecture Research GroupWorkshop on Binary Instrumentation and Applications San

2、 Jose, CA 10.22.2006,Outline,IntroductionBackground/TerminologySoftware-centric Fault DetectionProcess-Level RedundancyExperimental ResultsConclusion,Introduction,Process technology trends Single transistor error rate expected to stay close to constant Number of transistors is increasing exponential

3、ly with each generationTransient faults will be a problem for microprocessors!Hardware Approaches Specialized redundant hardware, redundant multi-threading Software Approaches Compiler solutions: instruction duplication, control flow checking Low-cost, flexible alternative but higher overheadGoal: L

4、everage available hardware parallelism in SMT and CMP machines to improve the performance of software transient fault tolerance,Background/Terminology,Types of transient faults (based upon outcome) Benign Faults Silent Data Corruption (SDC) Detected Unrecoverable Error (DUE) True DUE False DUESphere

5、 of Replication (SoR) Indicates the scope of fault detection and containment Input Replication Output Comparison,Software-centric Fault Detection,Most previous approaches are hardware-centric Even compiler approaches (e.g. EDDI, SWIFT) Software-centric able to leverage strengths of a software approa

6、ch Correctness is defined by software output Ability to see larger scope effect of a fault Ignore benign faults,Processor,Cache,Memory,Devices,Application,Libraries,Operating System,Hardware-centric Fault Detection,Software-centric Fault Detection,Software SoR,Hardware SoR,Process-Level Redundancy (

7、PLR),System Call Emulation Unit Creates redundant processes Barrier synchronize at all system calls Enforces SoR with input replication and output comparison Emulates system calls to guarantee determinism among all processes Detects and recovers from transient faults,App,Libs,App,Libs,App,Libs,SysCa

8、ll Emulation Unit,Operating System,Watchdog Alarm,Master Processonly processallowed to perform system I/O,Redundant Processesidentical address space,file descriptors, etc.not allowed to performsystem I/O,Watchdog Alarmoccasionally a processwill hangset at beginning of barriersynchronization to ensur

9、ethat all processes arealive,Enforcing SoR and Determinism,Input Replication All read events: read(), gettimeofday(), getrusage(), etc. Return value from all system callsOutput Comparison All write events: write(), msync(, etc. System call parametersMaintaining Determinism at System Calls Master pro

10、cess executes system call Redundant processes emulate it Ignore some: rename(), unlink() Execute similar/altered system call Identical address space: mmap() Process-specific data: open(), lseek(),Compare syscall type and cmd line parameters,Write cmd line parameters and syscall type to shmem,read(),

11、Write resulting file offset and read buffer to shmem,Copy the read buffer from shmem,lseek() to correct file offset,Master Process,Redundant Processes,Barrier,Example of handling a read() system call,Fault Detection and Recovery,PLR supports detection/recovery from multiple faults by increasing numb

12、er of redundant processes and scaling the majority vote logic,Type of Error,Detection Mechanism,Recovery Mechanism,Experimental Methodology,Use a set of the SPEC2000 benchmarks PLR prototype developed with Pin Intercept system calls to implement PLR Fault Injection Gather an instruction count profil

13、e Use profile to generate a test case Test case: an instruction and a particular execution of the instruction to fault Run with Pin in JIT mode and use IARG_RETURN_REGS to alter a random bit of the instructions source or destination registers Fault Coverage Use fault injector on test inputs generati

14、ng 1000 test cases per benchmark specdiff in SPEC2000 harness determines output correctness PLR Performance Run PLR (in Probe mode using Pin Probes) on reference inputs with two redundant processes 4-way SMP machine, each processor is hyper-threaded Use sched_set_affinity() to simulate various hardw

15、are platforms,Fault Coverage,Watchdog timeout very rare so not shown PLR detects all Incorrect and Failed cases Effectively detects relevant faults and ignores benign faults Floating point correctness question (ex. 168.wupwise, 172.mgrid) Actually different results but tolerable difference for specd

16、iff,Performance,Performance for single processor (PLR 1x1), 2 SMT processors (PLR 2x1) and 4 way SMP (PLR 4x1) Slowdown for 4-way SMP only 1.26x Should be better on a CMP with faster processor interconnect,Conclusion,Present a different way to use existing general purpose SMT and CMP machines for tr

17、ansient fault toleranceDifferentiate between hardware-centric and software-centric fault detection models Show how software-centric can be effective in ignoring benign faultsPLR on a 4-way SMP executes with only a 26% slowdown, a 36% improvement over the fastest compiler techniqueFuture Work Implementation in a run-time system allows for dynamically altering amount of fault tolerance Simple PLR model is presented; work on handling interrupts, shared memory, and threads (the tough one),Questions?,