JEDEC JESD69C-2017 Information Requirements for the Qualification of Silicon Devices.pdf

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1、JEDEC STANDARD Information Requirements for the Qualification of Silicon Devices JESD69C (Revision of JESD69B, October 2007) NOVEMBER 2017 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDE

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3、ucts, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their

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5、 represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims

6、 to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards

7、 and Documents for alternative contact information. Published by JEDEC Solid State Technology Association 2017 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this fil

8、e the individual agrees not to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid State Tec

9、hnology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 69C -i- INFORMATION REQUIREMENTS FOR THE QUALIFICATION OF SILICON DEVICES Introduction Customers utilize supplier informat

10、ion when performing device qualification. This information typically includes quality, reliability, electrical and mechanical performance data. In addition, customers frequently request the supplier to complete a profile, or fact sheet, on the device or device family being evaluated. This profile ma

11、y include information on the materials used within the device as well as the location of the devices manufacture or test. This profile, coupled with the above mentioned data elements, support the customers evaluation of a devices suitability for use in their application. JEDEC Standard No. 69C -ii-

12、JEDEC Standard No. 69C Page 1 INFORMATION REQUIREMENTS FOR THE QUALIFICATION OF SILICON DEVICES (From JEDEC Board Ballot JCB-99-10, JCB-06-57, JCB-07-92, and JCB-17-27, formulated under the cognizance of the JC-14.3 Committee on Silicon Devices Reliability Qualification and Monitoring.) 1 Scope This

13、 standard is intended to apply to silicon devices. This standard defines the requirements for the device qualification package which the supplier provides to the customer. It is intended to establish a minimum set of data elements, rather than to define the full range of possible customer informatio

14、n requests. Customers who require additional information will have to negotiate these requests with the supplier. This standard does not define which qualification method be followed (e.g., JESD47, JESD94, JP001, or JESD201), what tests must be performed, nor the qualification performance levels (e.

15、g., reliability or quality) that a device must satisfy. Rather, it establishes a set of data elements that describes the device. It requests the supplier to provide the test results of their qualification efforts. Customers are responsible for determining the extent to which supplier provided inform

16、ation will be used as part of their qualification process. 2 Reference documents JEP95, JEDEC Registered and Standard Outlines for Solid State and Related Products JESD22-A113, Preconditioning of Plastic Surface Mount Devices Prior to Reliability Testing JESD47, Stress Test Driven Qualification of I

17、ntegrated Circuits JESD78, IC Latch-Up Test JESD94, Application Specific Qualification Using Knowledge Based Test Methodology JESD201, Environmental Acceptance Requirements for Tin Whiskers Susceptibility of Tin and Tin Alloy Surface Finishes JP001, Foundry Process Qualification Guidelines JS-001, H

18、uman Body Model (HBM) - Component Level JS-002, Charged Device Model (CDM) - Device Level J-STD-020, Moisture/Reflow Sensitive Classification for Nonhermetic Solid State Surface Mount Devices J-STD-075, Classification of Passive and Solid State Devices for Assembly Processes J-STD-609, Marking, Symb

19、ols, and Labels of Leaded and Lead-Free Terminal Finished Materials Used in Electronic Assembly JEDEC Standard No. 69C Page 2 3 General requirements When requested, the supplier shall provide a qualification package to the customer. Based upon the customer/supplier agreed to completion date and the

20、actual completion of all testing and analysis, this qualification package shall be made available to the customer within two weeks of all work being completed. If a final report cannot be completed within 2 weeks a preliminary report should be made available in its place. The elements below should b

21、e completed, where applicable, for all devices that were utilized as part of the qualification, not only the device being qualified. This will enable generic or family data to be used in the qualification. The qualification package may be provided electronically or in a hard copy format and shall co

22、ntain the following: A: Device Identification B: General Information C: Die Fabrication D: Package Assembly E: Electrical Test F: Supporting Data Listed below is the minimum set of data elements for each of the six items listed above that are to be documented in the qualification report: A: DEVICE I

23、DENTIFICATION 1. Part Number and Revision: The suppliers part number and device revision level 2. Device Marking: The top side marking of the device. Include a description of any codes used. 3. Die Marking: The marking on the die which identifies the device. B: GENERAL INFORMATION (If the device has

24、 more than 1 die, state information for each die.) 1. Technology and Device Type: Technology identifier, minimum physical feature size and device family (e.g., 0.5um CMOS, 16M DRAM). 2. Package Type: The package style and other unique attributes (if applicable, JEP95). 3. Pin Count: Number of extern

25、al connections. 4. Die Size: Die dimension: length, width, and thickness (units). 5. Electrostatic Discharge (ESD) Rating: Human Body Model (HBM) rating per JS-001 and Charged Device Model (CDM) rating per JS-002. 6. Latch-up: Latch up immunity capability and other relevant information per JESD78 7.

26、 MSL Moisture Sensitivity Level: Moisture Sensitivity Rating of device per J-STD-020 and peak reflow temperature to which the rating applies. 8. PSL Process Sensitivity Level: Process Sensitivity Rating of device per J-STD-075 and any additional information necessary to describe the process sensitiv

27、ity(s). JEDEC Standard No. 69C Page 3 3 General requirements (contd) C: DIE FABRICATION (If the device has more than 1 die, state information for each die.) 1. Fabrication Process Identifier, if applicable: A unique code or description which identifies the specific fabrication process. 2. Fabricatio

28、n Supplier Name: If subcontracted, name of the subcontracted company that owns the fabrication site. If there are multiple fab suppliers, state all covered by this report. 3. Fabrication Location(s): The country, state (if applicable), and city where the device is fabricated. If there are multiple f

29、abs or fab lines at this location, state fab number/name and/or Line number/name. 4. Die Metallization and Number of Levels: Composition of the die metallization and number of separate levels of metallization. 5. Die Protective Coating: Composition and thickness of topmost level of protection and co

30、ating on the die which may include more than one layer (e.g. passivation layers, polyimide wafer coats, liquid dispensed die coats). 6. Bond Pad or UBM (Under Bump Metallurgy) Composition, Thickness and Pitch: Composition, thickness, and pitch of wirebond pad or UBM. 7. Die Substrate Material: Start

31、ing material (e.g., SOI, Si, epi). D: PACKAGE ASSEMBLY 1. Assembly Process Identifier, if applicable: A unique code or description which identifies the specific assembly process, if applicable. 2. Assembly Supplier Name: If subcontracted, name of the subcontracted company that owns the assembly site

32、. If there are multiple assembly suppliers, state all covered by this report. 3. Assembly Location(s): The country, state (if applicable), and city where the device is assembled. 4. Leadframe or Substrate Type: Base material, number of core and build up layers (substrates only), finish and critical

33、dimensions. 5. Die-to-Die and/or Die-to-Package Interconnect: Type (e.g., TAB, wire bond, flipchip), metal composition, dimensions. 6. Die Attach, if applicable: Material, process and/or die attach technique to attach die to leadframe/substrate or to another die. 7. Package Material and Flammability

34、 Rating if plastic: Package material or composition (e.g., mold compound, underfill, hermetic package) and flammability rating, if plastic. 8. Terminal Finish or Solder Ball Material: Composition and proportion of the material(s) used as terminal frame finish (including tin whisker mitigation techni

35、ques used on tin and tin alloy finishes) or solder ball (for BGAs) (e.g., J-STD-609). JEDEC Standard No. 69C Page 4 3 General requirements (contd) E: ELECTRICAL TEST 1. Electrical Test Supplier Name: If subcontracted, name of the subcontracted company that owns the electrical test site that performs

36、 final functional test. If there are multiple test suppliers, state all covered by this report. 2. Electrical Test Location: The country, state (if applicable), and city of final electrical test. F: SUPPORTING DATA Results of the Suppliers Internal Qualification: All tests performed to evaluate the

37、quality, reliability and mechanical performance of the device. This can include internal evaluations, user-specific requirements, in-process monitors, and process/product change requalifications. 1. Test Performed: Test method performed (e.g., JESD22-A104E, condition C) and stress conditions associa

38、ted with this test (e.g., temperature, voltage, humidity). 2. Test Vehicle(s): Device(s) used to generate qualification data (e.g., part number and revision level). 3. Preconditioning: Conditions used in the simulation of the device attach process prior to stress testing (e.g., JESD22-A113). 4. Burn

39、-in Conditions (if performed): If the product tested was burned-in prior to reliability stress testing, state the burn-in conditions (e.g., temperature, voltage, duration). 5. Sample Sizes: Number of samples used in the test and maximum number of failures allowed for acceptance. 6. Fail Criteria: Th

40、e method used to assess whether a device has passed or failed a given test (e.g., electrical testing, mechanical integrity). 7. Test Results: The number of devices which pass or fail the test criteria. 8. Duration: The number of hours, cycles, etc. which devices were subjected to during the test. 9.

41、 Failure Analysis Results: The summarized results of any physical analysis of failures including an identification of the root cause, failure mechanism, and corrective action. 10. Construction Analysis Results: Results of a construction analysis if one was performed (e.g., cross-section, C-SAM, x-ra

42、y, visual inspection, ball shear). JEDEC Standard No. 69C Page 5 3 General requirements (contd) If generic or family data was used (e.g., family qualification, library qualification, or qualification by similarity), the following information for the Test Vehicle(s) must be provided if it is differen

43、t from the device being qualified. a. Part Number and Revision b. Technology and Device Type c. Package Type d. Pin Count e. Fabrication Supplier Name f. Fabrication Location g. Assembly Supplier Name h. Assembly Location i. Die Protective Coating j. Leadframe or Substrate Type k. Die Attach l. Pack

44、age Material m. Terminal finish (including any tin whisker mitigation technique) or solder ball material JEDEC Standard No. 69C Page 6 Annex A (informative) Differences between JESD69C and JESD69B This annex briefly describes most of the changes made to entries that appear in this standard, JESD69C,

45、 compared to its predecessor, JESD69B (October 2007). If the change to a concept involves any words added or deleted (excluding deletion of accidentally repeated words), it is included. Some punctuation changes are not included. Page Description of change i Replaced the term “component” with “device

46、” throughout the document 1 In Clause 2, added reference s to JESD78, JS-001, JS-002, J-STD-075, and J-STD-609, and reordered the references alphabetically 2 In clause 3, after the initial list of 6 items, clarified that the data sets for each item are to be included in the qualification report 3 In

47、 clause 3B, added new item 5, ESD Rating; added new item 6, Latch-up; item 5 became item 7, and slightly modified its text; and added new item 8, Process Sensitivity Level 4 In clause 3D, item 8; added reference to J-STD-609 4 In clause 3F, item 1; added an example of how to describe the test method

48、 performed A.1 Differences between JESD69B and JESD69A Page Description of change 1 In Clause 1, 2ndparagraph; added JESD201 1 In Clause 2, added reference JESD201 3 In clause 3D, item 8; changed “Lead” to “Terminal” 3 In clause 3D, item 8; added “(including tin whisker mitigation techniques used on

49、 tin and tin alloy finishes)” 5 In clause 3; added item m Standard Improvement Form JEDEC JESD69C The purpose of this form is to provide the Technical Committees of JEDEC with input from the industry regarding usage of the subject standard. Individuals or companies are invited to submit comments to JEDEC. All comments will be collected and dispersed to the appropriate committee(s). If you can provide input, please complete this form and return to: JEDEC Attn: Publications Department 3103 North 10thStreet Suite 240 South Arlington, VA 22201-2107 Fax: 703.907.7583 1. I recomme