JEDEC JESD230B-2014 NAND Flash Interface Interoperability.pdf

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1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD230BJULY 2014JEDECSTANDARDNAND Flash Interface Interoperability (Revision of JESD2320A, August 2013)PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid Stat

2、e Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information NOTICEJEDEC standards and publications contain material that has been prepared, reviewed, and approvedthrough the JEDEC Board of Director

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4、 purchaser in selecting and obtaining with minimum delay theproper product for use by those other than JEDEC members, whether the standard is to be used eitherdomestically or internationally.JEDEC standards and publications are adopted without regard to whether or not their adoption mayinvolve paten

5、ts or articles, materials, or processes. By such action JEDEC does not assume any liability toany patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards orpublications.The information included in JEDEC standards and publications represents a sound approach t

6、o productspecification and application, principally from the solid state device manufacturer viewpoint. Within theJEDEC organization there are procedures whereby a JEDEC standard or publication may be furtherprocessed and ultimately become an ANSI standard.No claims to be in conformance with this st

7、andard may be made unless all requirements stated in thestandard are met.Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication shouldbe addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Documentsfor alternative contact

8、 information.Published byJEDEC Solid State Technology Association 20143103 North 10th StreetSuite 240 SouthArlington, VA 22201-2107This document may be downloaded free of charge; however JEDEC retains the copyright on this material.By downloading this file the individual agrees not to charge for or

9、resell the resulting material.PRICE: Contact JEDECPrinted in the U.S.A.All rights reservedJEDEC Standard No. 230BPage 1NAND FLASH INTERFACE INTEROPERABILITY(From JEDEC Board Ballot JCB-14-16, formulated under the cognizance of the JC-42.4 Subcommittee on Nonvolatile Memory Devices.)1ScopeThis standa

10、rd was jointly developed by JEDEC and the Open NAND Flash Interface Workgroup, hereafter referred to as ONFI. This standard defines a standard NAND flash device interface interoperability standard that provides means for system be designed that can support Asynchronous SDR, Synchronous DDR and Toggl

11、e DDR NAND flash devices that are interoperable between JEDEC and ONFI member implementations. 2 Terms, definitions, abbreviations and conventions 2.1 Terms and definitions address: A character or group of characters that identifies a register, a particular part of storage, or some other data source

12、 or destination. (Ref. ANSI X3.172 and JESD88.) NOTE 1 In a nonvolatile memory array, the address consists of characters, typically hexadecimal, to identify the row and column location of the memory cell(s). NOTE 2 For NAND nonvolatile memory devices, the row address is for a page, block, or logical

13、 unit number (LUN); the column address is for the byte or word within a page. NOTE 3 The least significant bit of the column address is zero for the source synchronous data interface. asynchronous: Describing operation in which the timing is not controlled by a clock. NOTE For a NAND nonvolatile mem

14、ory, asynchronous also means that data is latched with the WE_n signal for the write operation and the RE_n signal for the read operation. block: A continuous range of memory addresses. (Ref. IEC 748-2 and JESD88.) NOTE 1 The number of addresses included in the range is frequently equal to 2n, where

15、 n is the number of bits in the address. NOTE 2 For nonvolatile memories, a block consists of multiple pages and is the smallest addressable memory segment within a memory device for the erase operation. column: In a nonvolatile memory array, a series of memory cells whose sources and/or drains are

16、connected via a bit line. NOTE 1 Depending on the nonvolatile memory array, the bit line is accessed via the column select transistor, the column address decoder, or other decoding scheme. NOTE 2 In nonvolatile memory device, a column decoder accesses a bit (x1), byte (x8), word (x16), or Dword (x32

17、) either individually or within a page. NOTE 3 In a typical schematic of a memory array, the column is in the vertical direction. Dword (x32): A sequence of 32 bits that is stored, addressed, transmitted, and operated on as a unit within a computing system. NOTE 1 A Dword may be represented as 32 bi

18、ts, as two adjacent words, or as four adjacent bytes. When shown as bits, the least significant bit is bit 0 and the most significant bit is bit 31; the most significant bit is shown on the left. When shown as words, the least significant word (lower) is word 0 and the most significant (upper) word

19、is word 1. When shown as bytes, the least significant byte is byte 0 and the most significant byte is byte 3. NOTE 2 See Figure 1 for a description of the relationship between bytes, words, and Dwords. JEDEC Standard No. 230BPage 22.1 Terms and definitions (contd)latching edge: The rising or falling

20、 edge of a waveform that initiates a latch operation. NOTE 1 For a NAND nonvolatile memory the latching edge is the edge of the CK or DQS signal on which the contents of the data bus are latched for the source synchronous data interface. NOTE 2 For a NAND nonvolatile data cycles, the latching edge i

21、s both the rising and falling edges of the DQS signal. NOTE 3 For a NAND nonvolatile command and address cycles, the latching edge for the source synchronous interface is the rising edge of the CK signal. NAND defect area: A designated location within the NAND memory where factory defects are identi

22、fied by the manufacturer.NOTE 1 The location is a portion of either the first page and/or the last page of the factory-marked defect block, this defect area in each page is defined as (# of data bytes) to (# of data bytes + # of spare bytes -1). NOTE 2 For an 8-bit data access NAND memory device, th

23、e manufacturer sets the first byte in the defect area of the first or last page of the defect block to a value of 00h.NOTE 3 For a 16-bit data access NAND memory device, the manufacturer sets the first word in the defect area of the first or last page of the defect block to a value of 0000h.NAND non

24、volatile memory device: The packaged NAND nonvolatile memory unit containing one or more NAND targets. NOTE This is referred to as “device“ in this standard. NAND row address: An address referencing the LUN, block, and page to be accessed.NOTE 1 The page address uses the least significant row addres

25、s bits.NOTE 2 The block address uses the middle row address bits.NOTE 3 The LUN address uses the most significant row address bits.page: The smallest nonvolatile memory array segment, within a device, that can be addressed for read or program operations. page register: A register used to transfer da

26、ta from a page in the memory array for a read operation or to transfer data to a page in the memory array for a program operation. read request (for a nonvolatile memory): A data output cycle request from the host that results in a data transfer from the device to the host.source synchronous (for a

27、nonvolatile memory): Describing an operation in which the strobe signal (DQS) is transmitted with the data to indicate when the data should be latched. NOTE The strobe signal (DQS) is similar in concept to an additional data bus bit. status register (SRx): A register within a particular LUN containi

28、ng status information about that LUN. NOTE SRx refers to bit “x“ within the status register. target: A nonvolatile memory component with a unique chip enable (CE_n) select pin. word (x16): A sequence of 16 bits that is stored, addressed, transmitted, and operated on as a unit within a computing syst

29、em.NOTE 1 A word may be represented as 16 bits or as two adjacent bytes. When shown as bits, the least significant bit is bit 0 and the most significant bit is bit 15; the most significant bit is shown on the left. When shown as bytes, the least significant byte (lower) is byte 0 and the most signif

30、icant byte is byte 2. NOTE 2 See Figure 1 for a description of the relationship between bytes, words, and Dwords. JEDEC Standard No. 230BPage 32.2 Abbreviations DDR: Abbreviation for “double data rate“. LUN (logical unit number): The minimum memory array size that can independently execute commands

31、and report status. N/A: Abbreviation for “not applicable“. Fields marked as “na“ are not used. O/M: Abbreviation for Optional/Mandatory requirement. When the entry is set to “M“, the item is mandatory. When the entry is set to “O“, the item is optional. 2.3 Conventions 2.3.1 Active-low signals While

32、 the preferred method for indicating a signal that is active when low is to use the over-bar as in CE, the difficulty in producing this format has resulted in several alternatives meant to be equivalents. These are the use of a CE reverse solidus ( ) or the trailing underscore ( _ ) following the si

33、gnal name as in CE and CE_. In this publication “_n“ is used to indicate an active low signal (i.e. an inverted logic sense). 2.3.2 Signal names The names of abbreviations, initials, and acronyms used as signal names are in all uppercase (e.g., CE_n). Fields containing only one bit are usually refer

34、red to as the “name bit“ instead of the “name field“. Numerical fields are unsigned unless otherwise indicated. 2.3.3 Precedence in case of conflict If there is a conflict between text, figures, state machines, timing diagrams, and/or tables, the precedence shall be state machine, timing diagrams, t

35、ables, figures, and text. 2.4 Keywords Several keywords are used to differentiate between different levels of requirements or suggestions. mandatory: A keyword indicating items to be implemented as defined by a standard. Users are required to implement all such mandatory requirements to ensure inter

36、operability with other products that conform to the standard. may: A keyword that indicates flexibility of choice between stated alternatives or possibly nothing with no implied preference. optional: A keyword that describes features that are not required by the specification. However, if any option

37、al feature defined by the specification is implemented, that feature shall be implemented in the way defined by the specification.reserved: A keyword indicating reserved bits, bytes, words, fields, and opcode values that are set-aside for future standardization. Their use and interpretation may be s

38、pecified by future extensions to this or other specifications. A reserved bit, byte, word, or field may be cleared to zero or in accordance with a future extension to this publication. A host should not read/use reserved information.shall: A keyword indicating a mandatory requirement. should: A keyw

39、ord indicating flexibility of choice with a strongly preferred alternative. This is equivalent to the phrase “it is recommended“. JEDEC Standard No. 230BPage 42.5 Byte, Word and Dword RelationshipsFigure 1 illustrates the relationship between bytes, words and DwordsFigure 1 Byte, word and Dword rela

40、tionships765 4 3 2 1 0Byte15141312111098765 4 3 2 1 0Word Byte 1 Byte 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18171615141312111098765 4 3 2 1 0DwordWord 1 Word 0Byte 3 Byte 2 Byte 1 Byte 0 JEDEC Standard No. 230BPage 52.6 Pin descriptionTable 1 Pin descriptionNameInput/OutputDescriptionIO0 IO7( IO1

41、5)DQ0 DQ7DQ0_x DQ7_xI/ODATA INPUTS/OUTPUTS These signals are used to input command, address and data, and to output data during read operations. The signals float to high-z when the chip is deselected or when the outputs are disabled. IO0 IO15 are used in a 16-bit wide target configuration. With mul

42、ti channel support, IO0_0IO7_0 and IO0_1IO7_1 are used for IOs of channel 0 and IOs of channel 1 respectively. Also known as DQ0DQ7 for Toggle DDR and Synchronous DDR. The number after the underscore represents the channel. For example, DQ0_0 indicates DQ0 of channel-0 and DQ0_1 does DQ0 of channel-

43、1.CLE_x ICOMMAND LATCH ENABLEThe CLE_x signal is one of the signals used by the host to indicate the type of bus cycle (command, address, data).ALE_x IADDRESS LATCH ENABLEThe ALE_x signal is one of the signals used by the host to indicate the type of bus cycle (command, address, data).CEx_x_n ICHIP

44、ENABLEThe CEx_x_n input is the target selection control. When CEx_x_n is high and the target is in the ready state, the target goes into a low-power standby state. When CEx_x_n is low, the target is selected. The number after the first underscore represents the channel. For example, CE0_0_n indicate

45、s CE0_n of channel-0 and CE0_1_n does CE0_n of channel-1.WE_x_n IWRITE ENABLEThe WE_x_n input controls writes to the I/O port. For Asynchronous SDR Data, commands, addresses are latched on the rising edge of the WE_x_n pulse. For Toggle DDR commands, addresses are latched on the rising edge of the W

46、E_x_n pulse.R/B_x_n OREADY/BUSY OUTPUTThe R/B_x_n output indicates the status of the target operation. When low, it indicates that one or more operations are in progress and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is dese

47、lected or when outputs are disabled.RE_x_n(RE_x_t)IREAD ENABLEThe RE_x_n input is the serial data-out control. For Asynchronous SDR Data is valid tREA after the falling edge and for Toggle DDR Data is valid after the falling edge & rising edge of RE_x_n which also increments the internal column addr

48、ess counter by each one.RE_x_c IComplement of Read EnableThis is the complementary signal to Read EnableDQS_x(DQS_x_t)I/OData StrobeThe data strobe signal that indicates the data valid window for Toggle DDR and Synchronous DDR data interface. Output with read data, input with write data. Edge-aligne

49、d with read data, centered in write data. DQS_x_c I/OComplement of Data StrobeThis is the complementary signal to Data Strobe.W/R_x IWrite/Read DirectionThe Write/Read Direction signal indicates the owner of the DQ bus and DQS signal in the Synchronous DDR data interface. This signal shares the same pin as RE_x_n in the asynchronous data interface.JEDEC Standard No. 230BPage 6NOTE 1 All Vcc, VccQ and Vss pins of each device shall be connected to common power supply outputs.NOTE 2 All Vcc, VccQ, Vss and VssQ shall not be disconnected.3VcQLow