JEDEC JESD22-B108B-2010 Coplanarity Test for Surface-Mount Semiconductor Devices.pdf
《JEDEC JESD22-B108B-2010 Coplanarity Test for Surface-Mount Semiconductor Devices.pdf》由会员分享,可在线阅读,更多相关《JEDEC JESD22-B108B-2010 Coplanarity Test for Surface-Mount Semiconductor Devices.pdf(14页珍藏版)》请在麦多课文档分享上搜索。
1、JEDEC STANDARD Coplanarity Test for Surface-Mount Semiconductor Devices JESD22-B108B (Revision of JESD22-B108A, January 2003) SEPTEMBER 2010 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JE
2、DEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of pr
3、oducts, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not the
4、ir adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publicatio
5、ns represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No clai
6、ms to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or www.jedec.org
7、 Published by JEDEC Solid State Technology Association 2010 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell
8、 the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies through entering into
9、a license agreement. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or call (703) 907-7559 JEDEC Standard No. 22-B108B Page 1 Test Method B108B (Revision of B108A) TEST METHOD B108B COPLANARITY TEST FOR SURFACE-MOUNT
10、 SEMICONDUCTOR DEVICES (From JEDEC Board Ballot JCB-02-122 and JCB-10-33, formulated under the cognizance of the JC-14.1 Subcommittee on Reliability Test Methods for Packaged Devices.) 1 Scope The purpose of this test is to measure the deviation of the terminals (leads or solder balls) from coplanar
11、ity at room temperature for surface-mount semiconductor devices. This test method is applicable for inspection and device characterization. If package warpage or coplanarity is to be characterized at reflow soldering temperatures, then JESD22-B112 should be used. 2 Apparatus The equipment utilized i
12、n this test shall be capable of measuring the deviation of the terminals from coplanarity to specified tolerances as determined by the applicable procurement document. Equipment must be capable of measurement accuracies within +/- 10% of the specified deviation. 3 Terms and definitions deviation fro
13、m coplanarity: The distance between the intended contact point of the terminal and the established seating plane or regression plane. regression plane: A plane that (1) passes through the apex of the terminal that has the greatest perpendicular distance from the package substrate, and (2) is paralle
14、l to the best-fit plane through the apexes of all terminals determined using the method of least squares. NOTE The regression plane may be used to emulate the package coplanarity during reflow soldering at the point of surface mounting. seating plane: The plane formed by the three terminal apexes th
15、at exhibit the greatest perpendicular distance from the package substrate, provided that the triangle formed by those three apexes encompasses the projection of the center of gravity (COG) of the component. terminal: An externally available point of connection. terminal apex: The point on the termin
16、al surface that exhibits the greatest perpendicular distance from the package substrate. JEDEC Standard No. 22-B108B Page 2 Test Method B108B (Revision of B108A) 4 Reference JEP95, Design Guide 4.17, BGA (Ball Grid Array) Package Measuring and Methodology. JESD22-B112, Package Warpage Measurement of
17、 Surface-Mount Integrated Circuits at Elevated Temperature. 5 Procedure There are two methods suitable for measurement of coplanarity. They are the seating plane method and the regression plane method. Each procedure produces a coplanarity value within the limits of error expected for this measureme
18、nt. Traditionally, the seating plane method of measuring deviation from coplanarity is preferred. However, the regression plane method is an acceptable alternative provided the results obtained correlate to those of the seating plane method. 5.1 Seating plane method The following procedures are to b
19、e used: a) Care must be taken in handling to ensure no damage to the terminals. b) The seating plane shall be in the horizontal position with the device placed as shown in Figure 1. It is preferable that the component terminals be measured while the component is in the dead-bug (leads-up) position.
20、c) When coplanarity measurements are made, there shall be no external forces applied to the device. d) Determine the apex of each and every terminal . e) Determine the three terminal apexes that exhibit the greatest perpendicular distance from the substrate. These form the seating plane, see Figure
21、1. Projectionof C.O.G.Figure 1 Three apexes forming the seating plane and encompassing projection of C.O.G JEDEC Standard No. 22-B108B Page 3 Test Method B108B (Revision of B108A) 5 Procedure (contd) 5.1 Seating plane method (contd) f) The triangle of terminals defining the seating plane must encomp
22、ass the projection of the center of gravity (C.O.G.) in order to constitute a valid seating plane. If the plane is not considered valid, the next terminal with the greatest perpendicular distance from the substrate shall be considered as a candidate terminal to be used in forming a valid seating pla
23、ne. If the seating plane triangle passes through the package center of gravity, the seating plane will be valid, but multiple seating planes could exist. If multiple seating planes do exist, the seating plane yielding the worst-case measurement shall be used for coplanarity determination. g) Deviati
24、on from coplanarity is measured as the distance from the seating plane to the apex of each and every terminal. The largest measurement is the deviation from coplanarity; see Figure 2 and Figure 3 (BGA versus leaded terminal). h) Report that the deviation from coplanarity was determined by the seatin
- 1.请仔细阅读文档,确保文档完整性,对于不预览、不比对内容而直接下载带来的问题本站不予受理。
- 2.下载的文档,不会出现我们的网址水印。
- 3、该文档所得收入(下载+内容+预览)归上传者、原创作者;如果您是本文档原作者,请点此认领!既往收益都归您。
下载文档到电脑,查找使用更方便
10000 积分 0人已下载
下载 | 加入VIP,交流精品资源 |
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- JEDECJESD22B108B2010COPLANARITYTESTFORSURFACEMOUNTSEMICONDUCTORDEVICESPDF

链接地址:http://www.mydoc123.com/p-807094.html