JEDEC JESD22-B106E-2016 Resistance to Solder Shock for Through-Hole Mounted Devices.pdf

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1、JEDEC STANDARD Resistance to Solder Shock for Through-Hole Mounted Devices JESD22-B106E (Revision of JESD22-B106D, April 2008) NOVEMBER 2016 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JE

2、DEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of pr

3、oducts, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not the

4、ir adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publicatio

5、ns represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No clai

6、ms to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standar

7、ds and Documents for alternative contact information. Published by JEDEC Solid State Technology Association 2016 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this f

8、ile the individual agrees not to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid State T

9、echnology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard 22-B106E Page 1 Test Method B106E (Revision of Test Method B106D) TEST METHOD B106E RESISTANCE TO SOLDER SHOCK FOR THROUGH-H

10、OLE MOUNTED DEVICES (From JEDEC Board Ballot JCB-98-98, JCB-05-12, JCB-08-09, and JCB-16-46, formulated under the cognizance of JC-14.1 Committee on Reliability Test Methods for Packaged Devices.) 1 Scope This test method is used to determine whether solid state devices can withstand the effect of t

11、he temperature shock to which they will be subjected during soldering of their leads in a solderwave process and/or solder fountain (rework/replacement) process. The heat is conducted through the leads into the device package from solder heat at the reverse side of the board. This test method shall

12、not be used to simulate wave soldering of surface mount device packages that are glued onto the same side of the board as the solder wave and are fully submerged into the solder wave. The test method for simulating SMT devices through the wave is JESD22-A111, Evaluation Procedure for Determining Cap

13、ability to Bottom Side Board Attach by Full Body Solder Immersion of Small Surface Mount Solid State Devices. In order to establish a standard test procedure for the most reproducible methods, the solder dip method is used because of its more controllable conditions. This procedure will determine wh

14、ether devices are capable of withstanding the soldering temperature encountered in printed wiring board assembly operations, without degrading their electrical characteristics or internal connections. This test is destructive and may be used for qualification, lot acceptance and as a product monitor

15、. 2 Apparatus 2.1 Solder Pot A solder pot of sufficient size to contain at least 0.91 kg (2 lbs.) of solder shall be used. Its dimensions shall allow immersion of the leads to the depth specified in 4.3 without touching the bottom of the pot. The apparatus shall be capable of maintaining the solder

16、at the temperature specified in 4.2 at the location where the device leads make contact with the solder. 2.2 Dipping Device A mechanical dipping device shall be used that is capable of controlling the rates of immersion and emersion of the leads and providing the dwell time specified in 4.3. JEDEC S

17、tandard 22-B106E Page 2 Test Method B106E (Revision of Test Method B106D) 2 Apparatus (contd) 2.3 Heatsinks or shielding If a heatsink or shielding is typically applied to the device prior to the solderwave process, then such heatsinks or shielding shall be attached to the devices prior to this test

18、 and shall be specified in the applicable procurement document. 3 Materials 3.1 Solder The solder shall conform to J-STD-006, Requirements for Electronic Grade Solder Alloys and Fluxed and Non-Fluxed Solid Solders for Electronic Soldering Applications. SnPb alloy composition: Sn60Pb40 or Sn63Pb37 (S

19、n 1%). Pb-free solder alloy composition: Sn95.5Ag3.9Cu0.6, allowing variation of the Ag content between 3.0 4.0 wt% and Cu content between 0.5 1.0 wt%. Other lead-free alloy compositions may be used by agreement between user and supplier. 4 Procedure 4.1 Special preparation of specimens Any special

20、preparation of the specimens prior to testing shall be as specified in the individual specification. This preparation may include operations such as bending, or other relocation of leads, and the attachment of heat sinks or protective shielding prior to solder dipping. 4.2 Preparation of the solder

21、bath The dross shall be skimmed from the surface of the molten solder just prior to dipping the part. 4.2.1 SnPb solder bath temperature The SnPb solder bath shall be maintained at a temperature of 260 C 5 C as measured per 2.1. 4.2.2 Pb-free solder bath temperature The Pb-free solder bath shall be

22、maintained at a temperature of 270 C 5 C as measured per 2.1. JEDEC Standard 22-B106E Page 3 Test Method B106E (Revision of Test Method B106D) 4 Procedure (contd) 4.3 Solder dip The part shall be attached to the dipping device (see 2.2) and the leads immersed in the molten solder to within 1 mm (0.0

23、4“) of the body of the device under test. The immersion and emersion rates shall be 25 6 mm (1 “) per second. See sections 4.3.1 and 4.3.2 for the appropriate dwell time in the solder. After the dipping process, the part shall be allowed to cool in air. 4.3.1 SnPb solder bath dip dwell time The dwel

24、l time for a SnPb solder bath shall be 10 +2/-0 seconds. 4.3.2 Pb-free solder bath dip dwell time 4.3.2.1 Pb-free solder bath dip dwell time The dwell time for a Pb-free solder bath shall be 7 +2/-0 seconds. 4.3.2.2 Optional Pb-free solder bath dip dwell time for solder fountain rework If the part m

25、ust survive a solder fountain rework process, the dwell time for a Pb-free solder bath shall be 15 +2/-0 seconds. 4.4 Precautions Prior to and after the solder immersion, precautionary measures shall be taken to prevent undue exposure of the part to the heat from the solder bath. In addition, care m

26、ust be taken to prevent thermal shocking the part when placed into flux removal agent. If there is some concern that the heat from the solder bath may be affecting the results of the test, the test may be performed by inserting the leads through holes in a test board to shield the body of the device

27、 from the heat of the solder bath, thus better simulating typical soldering conditions. 4.5 Measurements Hermeticity tests for hermetic devices, visual examination, and electrical measurements, that consist of parametric and functional tests shall be made as specified in the applicable procurement d

28、ocument. JEDEC Standard 22-B106E Page 4 Test Method B106E (Revision of Test Method B106D) 4.6 Failure criteria A device shall be defined as a failure if hermeticity for hermetic devices cannot be demonstrated, if parametric limits are exceeded, or if functionality cannot be demonstrated under nomina

29、l and worst case conditions specified in the applicable procurement document. Mechanical damage such as cracking, chipping, or breaking of the package, (10X - 20X magnification), will also be considered a failure provided such damage was not induced by fixturing or handling. 5 Summary The following

30、details shall be specified in the applicable procurement document: a) The use of heatsinks or shielding, if applicable (see 2.3). b) Special preparation of specimens, if applicable (see 4.1). c) Temperature of solder bath, if other than as specified in 4.2. d) Time and depth of immersion, if other t

31、han as specified in 4.3, and if 4.3.2.2 is required. e) Failure criteria per 4.6 or other used. f) Sample size and quality level. JEDEC Standard 22-B106E Page 5 Test Method B106E (Revision of Test Method B106D) Annex A (informative) Process information collected to generate this revision For revisio

32、n D of B106, the Pb-free process data stated below were collected. These data state that solder wave pot temperatures can be 10 C higher for Pb-free solder than for eutectic SnPb solder, especially for relatively thick, complex boards. However, data were not yet available for the largest and most co

33、mplex boards. For revision E, with Pb-free processes now in full production for most member companies, a follow-up survey was performed in 2015 to determine conditions for thick, complex boards and if there were any significant changes in process conditions. The survey includes conditions for boards

34、 up to 3.2 mm thick and up to 28 layers. The results of the survey reaffirmed that the conditions stated in this test method were still valid. Solder pot temperatures for initial attach of solid state devices on large boards were in the range that would be covered by the current 265 +/-5 C condition

35、s in this test method. Dwell times were found to be 3 to 7 seconds for large boards, for both single and dual wave systems, which are slightly longer than the previous survey, but still covered by the requirements of this test method. Table A.1 Pb-Free Wave Company Solder pot temperature Dwell time

36、Board thicknessPreheat temperature, board and/or component temp. Preheat duration Other comments A 265 +/-5 C 3 to 4 seconds 2.0 mm (79 mils),6 layer 120 C comp. lead 0.7 m/min conveyor265 +/-5 C 5 seconds 2.2 mm (87 mils),14 layer 110 C comp. lead 0.6 m/min conveyorB 265 +/-5 C 2-3 seconds 1.6 to 2

37、.0mm (63 to 79 mils) 140 C, board max. 1 m/min conveyor, C 265 +/-5 C 3 to 6.5 seconds thick (90 mils) 140 C, comp. body 260 +/-5 C 2 to 4 seconds thin (62 mils) 125 C, comp body single wave D 265-270 C 2-5 sec., single wave 62 mils 110-140 C comp. body 2 minutes E 260-265 C 3-8 sec 63 to 135 mils 1

38、10-130 C PWB topside 2-3 minutes Table A.2 Pb-Free Rework (solder fountain) Company Solder pot temperature Dwell time / contact with solder pot # of solder pot contacts for replacement of component Board thicknessPreheat temperature, board and/or component temp. Preheat duration A 265 +/-5 C 5-10 se

39、conds, (8-10 sec. typical) 2 typical, but could be 3 62 mils 150 C board and comp. body 15 minutes in oven C 277 +/- 5 C Depends on component type and board thickness; up to 25 sec for 62 mils, 45 sec for 93 mils & up Most (85%) of DT boards rework is due to lead not through (or tilt) so component i

40、s not really replaced just re-seated. 62 mils 140 C for 62 mil thick boards 145 C for 93 mils and thicker boards 5 minutes in oven D 265 +/-5 C 5-10 seconds, (8-10 sec. typical) 2 typical, but could be 3 62 mils 150 C board and comp. body 15 minutes in oven E 271-277 C 10-15 seconds 1 contact 62 - 1

41、35 mils 150 C (board & comp.) time to ramp up to 150 CThe conditions stated in 4.2.2 and 4.3.2 are based on the data in the Table A.1 and Table A.2. JEDEC Standard 22-B106E Page 6 Test Method B106E (Revision of Test Method B106D) Annex A (informative) Process information collected to generate this r

42、evision (contd) The total dwell time and the preheat conditions for Pb-free solder fountain rework are more severe than initial attach, and the working group concluded that this test method needed to provide test conditions to cover the rework process. In gathering the data from multiple companies,

43、the working group asked each company what criteria were used in determining when solder fountain rework would be used versus hand soldering. The working group found that multiple factors determined the method used. There was no direct correlation between the size of the package being reworked and th

44、e method used. For these reasons, it was determined that this revision should include optional conditions for parts that need to be qualified for solder fountain rework. JEDEC Standard 22-B106E Page 7 Test Method B106E (Revision of Test Method B106D) Annex B (informative) Differences between JESD22-

45、B106E and JESD22-B106D This annex briefly describes most of the changes made to entries that appear in this standard, JESD22-B106E, compared to its predecessor, JESD22-B106D (April 2008). If the change to a concept involves any words added or deleted (excluding deletion of accidentally repeated word

46、s), it is included. Some punctuation changes are not included. Page Description of change 1 Clause 2.1, added clarity on where solder temperature to be measured. 2 Clause 4.1, removed reference to preheat. 3 Clause 4.4, added paragraph to allow for testing with devices mounted on test board. 5 Annex

47、 A, added paragraph to discuss results from 2015 industry survey. JEDEC Standard 22-B106E Page 8 Test Method B106E (Revision of Test Method B106D) Rev. 9/02 Standard Improvement Form JEDEC JESD22-B106E The purpose of this form is to provide the Technical Committees of JEDEC with input from the indus

48、try regarding usage of the subject standard. Individuals or companies are invited to submit comments to JEDEC. All comments will be collected and dispersed to the appropriate committee(s). If you can provide input, please complete this form and return to: JEDEC Attn: Publications Department 3100 Nor

49、th 10thStreet Suite 240S Arlington, VA 22201-3834 Fax: 703.907.7583 1. I recommend changes to the following: Requirement, clause number Test method number Clause number The referenced clause number has proven to be: Unclear Too Rigid In Error Other 2. Recommendations for correction: 3. Other suggestions for document improvement: Submitted by Name: Phone: Company: E-mail: Address: City/State/Zip: Date: