EN 60191-6-6-2001 en Mechanical Standardization of Semicondutor Devices Part 6-6 General Rules for the Preparation of Outline Drawings of Surface Mounted Semiconductor Device Packa.pdf

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1、BRITISH STANDARD Mechanical standardization of semiconductor devices - Part 6-6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine pitch land grid array (FLGA) The European Standard EN 60191-6-6:2001 has the status of a Bri

2、tish Standard ICs 31.080.10 01.100.25 NO COPYING WITHOUT BSI PERMISSION EXCEPT AS PERMITTED BY COPYRIGHT LAW BS EN IEC 60 191-6-6200 1 60 191-6-6:200 1 BS EN 60191-6-62001 Amd. No. Date National foreword Comments This British Standard, having been prepared under the direction of the Electrotechnicai

3、 Sector Policy and Strategy Committee, was published under the authority of the Standards Policy and Strategy Committee on 5 September 2001 This British Standard is the official English language version of EN 60191-6-6:2001. It is identical with IEC 60191-6-6:2001. The UK participation in its prepar

4、ation was entrusted by Technical Committee EPL/47, Semiconductor devices, to Subcommittee EPL/47/4, Mechanical standardization of semiconductor devices, which has the responsibility to: - - aid enquirers to understand the text; present to the responsible internationalEuropean committee any enquiries

5、 on the interpretation, or proposals for change, and keep the UK interests informed; monitor related international and European developments and promulgate them in the UK. - A list of organizations represented on this committee can be obtained on request to its secretary. From 1 January 1997, all IE

6、C publications have the number 60000 added to the old number. For instance, IEC 27-1 has been renumbered as IEC 60027-1. For a period of time during the change over from one numbering system to the other, publications may contain identifiers from both systems. Cross-references The British Standards

7、which implement international or European publications referred to in this document may be found in the BSI Standards Catalogue under the section entitled “International Standards Correspondence Index”, or by using the “Find“ facility of the BSI Standards Electronic Catalogue. A British Standard doe

8、s not purport to include all the necessary provisions of a contract. Users of British Standards are responsible for their correct application. Compliance with a British Standard does not of itself confer immunity from legal obligations. Summary of pages This document comprises a front cover, an insi

9、de front cover, the EN title page, pages 2 to 13 and a back cover. The BSI copyright date displayed in this document indicates when the document was last issued. O BSI 5 September 2001 ISBN O 580 38393 8 EU ROPEAN STAN DARD EN 60191-6-6 NORME EUROPENNE EUROPISCHE NORM July 2001 ICs 31.080.01 English

10、 version Mechanical standardization of semiconductor devices Part 6-6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine pitch land grid array (FLGA) (IEC 60191-6-612001) Normalisation mcanique des dispositifs semi-conducte

11、urs Partie 6-6: Rgles gnrales pour la prparation des dessins dencombrement des dispositifs semiconducteurs pour montage en surface - Guide de conception des dispositifs FLGA (CE1 601 91-6-62001) Mechanische Normung von Halbleiterbauelementen Teil 6-6: Allgemeine Regeln fr die Erstellung von Gehuseze

12、ichnungen von SMD-Halbleitergehusen - Konstru ktionsleitfaden fr Feinraster- Land-Grid-Array (FLGA) (I EC 601 91 -6-612001 ) This European Standard was approved by CENELEC on 2001-0501. CENELEC members are bound to comply with the CEWCENELEC Internal Regulations which stipulate the conditions for gi

13、ving this European Standard the status of a national standard without any alteration. Up-to-date lists and bibliographical references concerning such national standards may be obtained on appiication to the Central Secretariat or to any CENELEC member. This European Standard exists in three official

14、 versions (English, French, German). A version in any other language made by translation under the responsibility of a CENELEC member into its own language and notified to the Central Secretariat has the same status as the official versions. CENELEC members are the national electrotechnical committe

15、es of Austria, Belgium, Czech Republic, Denmark, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Netheriands, Noway, Portugal, Spain, Sweden, Switzerland and United Kingdom. CENELEC European Committee for Electrotechnical Standardization Comit Europen de Normalisation Electrot

16、echnique Europisches Komitee fr Elektrotechnische Normung Central Secretanat: rue de Stassart 35, B - 1050 Brussels 0 2001 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members. Ref. No. EN 60191-6-6:2001 E EN 60191-6-6:2001 Foreword The text of doc

17、ument 47D/404/FDIS, future edition 1 of IEC60191-6-6, prepared by SC470, Mechanical standardization of semiconductor devices, of IEC TC 47, Semiconductor devices, was submitted to the IECCENELEC parallel vote and was approved by CENELEC as EN 60191-6-6 on 2001-05-01. The following dates were fixed:

18、2 - latest date by which the EN has to be implemented at national level by publication of an identical national standard or by endorsement - latest date by which the national standards conflicting with the EN have to be withdrawn Annexes designated “normative“ are part of the body of the standard. I

19、n this standard, annex ZA is normative. Annex ZA has been added by CENELEC. (dop) 2002-02-01 (dw) 2004-05-01 En do rse me nt not ice The text of the International Standard IEC60191-6-6:2001 was approved by CENELEC as a European Standard without any modification. EN 60191-6-6:2001 INTRODUCTION The de

20、mand for area array style packages exists because of the multi-functions and high performance of electrical equipment. The objective of this design guide is to standardize outlines and to get interchangeability of FLGA packages. The terminal pitch and package outlines of these fine-pitch array packa

21、ges are smaller than those of LGA packages. BSI 5 September 2001 3 EN 60191-6-6:2001 MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES - Part 6-6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine-pitch land grid array (F

22、LGA) I Scope This part of IEC 60191 provides common outline drawings and dimensions for all types of structures and composed materials of fine-pitch land grid array (hereinafter called FLGA) whose terminal pitch is less than, or equal to, 0,80 mm and whose package body outline is square. 2 Normative

23、 references The following normative documents contain provisions which, through reference in this text, constitute provisions of this part of IEC 60191. For dated references, subsequent amendments to, or revisions of, any of these publications do not apply. However, parties to agreements based on th

24、is part of IEC 60191 are encouraged to investigate the possibility of applying the most recent editions of the normative documents indicated below. For undated references, the latest edition of the normative document referred to applies. Members of IEC and IS0 maintain registers of currently valid I

25、nternational Standards. IEC 601 91 (all parts), Mechanical standardization of semiconductor devices 3 Definitions For the purposes of this part of IEC 60191, the following definitions, as well as those given in the other parts of this standard, apply. 3.1 flanged type type whose package body size (b

26、ody length and width) consists of its own flange composed around the encapsulation or lid 3.2 type of real chip size type whose package body size (body length and width) consists of an encapsulation around the real chip only 3.3 FLGA packages with metal lands or metal bumps of which the terminal hei

27、ght is less than, or equal to, 100 pm, and whose terminal pitch is less than, or equal to, 0,80 mm, positioned in an array on the base plane of the package as external terminals This package structure makes it possible to surface-mount the packages to the printed circuit board 4 BSI 5 September 2001

28、 EN 60191-6-62001 3.4 material designation FLGA packages are classified according to the following two material designations: 3.4.1 plastic type (P-FLGA) plastic-type classification is assigned to packages which consist of resin substrate as interposer material (for example, glass-epoxy, poly-imid)

29、3.4.2 ceramic type (C-FLGA) ceramic-type classification is assigned to packages which consist of ceramic substrate as interposer material BSI 5 September 2001 5 EN 60191-6-62001 6 Even type nE UT - C B o o o o o o o 0;o o o 08 00 o o o o o o o 010 o o O0 o o o o o o o o o oio o o O0 O0 o o o o o o o

30、 oio o o O0 O0 o o o o o o o ojo o o O0 O0 o o o o o o o oio o o o o o o .9.00-.+ 0 0 0 0 0 0 pta o o o o o o oio o o o o o o o o o o o o o ojo o o O0 o o o 00000000 O0 O000 o o o o o o O0 ojo o o o o o o o o o o o o o o oio o o O0 O0 o o o o O0 O0 oio o o o o o o o o o o o o o o oio o o o o o o o A

31、 v IEC 300/0i Design guide for fine-pitch land grid array family Fine-pitch land grid array tamiiy IEC 60191 BSI 5 September 2001 EN 60191-6-6:2001 NOTE 1 Zone of a visible index on the top surface. NOTE 2 Datum A and B are the axes defined by the terminal positions indicated with datum targets. NOT

32、E 3 Primary datum S and seating plane to be defined by the method of least squares of spherical crowns of terminals. BSI 5 September 2001 7 EN 60191-6-6:2001 rable I - Group . . Dimensions appropriate to mounting and interchangeability Limits to be observed Recommended values for the dimensions mm R

33、ef. Note - Max. Min. lorn. X - n nD nE X X - 1 A A max. = 1.20. 1.70, 2,OO Includes heat slug Includes package warpage and tilt X Al X Al max. = 0.10 Ob X X X 4t ceramic FLGA (C-FLGA) Min. Nom. Max. at e = 0,80 0,451 0.50 0,55 at e = 0,65 0.35 0,40 0.45 at e = 0.50 0,25 0,30 0.35 at e = 0,40 0,20 0,

34、25 0.30 4t plastlc FLGA (P-FLGA) Min. Nom. Max. at e = 0,80 0,35 0.40 0.45 at e = 0.65 0.28 0.33 0.38 at e = 0.50 0.20 0.25 0,30 at e = 0,40 0.15 0,20 0.25 X 4t flanged type D = 4,O. 5.0. 6.0. 7.0, 8.0, 9,O. 10,O. 11.0, 12,O. 13,0, 14,O. 15.0. 16.0. 17,O. 18.0, 19.0, 20.0. 21,O 41 type of real chip

35、size D = from 3.1 to 21,O Dimension range shows nominal value X At flanged type E = 4,O. 5,0, 6.0, 7.0, 8,0, 9,0, 10,0, 11.0, 12.0, 13.0, 14,O. 15,O. 16.0, 17,O. 18.0, 19,O. 20.0, 21.0 At type of real chip size from 3.1 to 21.0 E = Dimension range shows nominal value e = 0.80, 0.65, 0.50, 0,40 v = 0

36、.15 Includes burrs X X at e = 0,80 at e = 0.65 at e = 0,50 at e = 0.40 w = 0,20 w = 0.20 w = 0.20 w = 0.15 X at e = OJO at e = 0.65 at e = 0.50 at e = 0.40 x = 0,08 x = 0.08 x = 0.05 x = 0.05 8 BSI 5 September 2001 Limit: to be c Nom. EN 60191-6-6:2001 Table 1 - (continued) JSeNed I Recommended valu

37、es I Note I for the dimensions mm X at e = 0,80 y = 0,lO y = 0,lO y = 0,08 y = 0,08 at e = 0.65 at e = 0.50 at e = 0.40 X Yi = 02 NOTE 1 The values stipulated by the mathematical expression should be applied to the individual overall dimensional standards. NOTE 2 Symbol n refers to the total number

38、of terminal positions. Table 2 - Group 2: Dimensions appropriate to mounting and gauging a See note 1 of table I. BSI 5 September 2001 9 EN 60191-6-62001 Max. X - Ref. for the dimensions Note mm A max. = 1,20. 1.70. 2.00 Includes heat slug A - Min. - Dl D Y4 X Table 3 -Group 3: Dimensions appropriat

39、e to automated handling y4 = 0.2 Yom. X ZD = (D - e x (nD - 1)/2 X X - 1s X ZE = (E -e x (nE - 1)/2 Includes package warpage and tilt DIE = 4,0, 5,O. 6.0. 7,0, 8.0, 9.0, 10.0, I 11.0. 12,0, 13.0. 14.0, 15,O. 16.0, I I 17.0, 18.0, 19.0, 20.0. 21,O I Table 4 - Group 4: Dimensions for information only

40、Limits to be observed Recommended values for the dimensions mm I Ref. 1-1 Min. Nom. Max. Note 10 BSI 5 September 2001 EN 60191-6-62001 Table 5 - Dimensions and bail matrix Maximum matrix row family Maximum matrix - 1 row family Maximum matrix - 2 row family e = 0,80 ExD 4 x4 5x5 6x6 7 x7 8x8 9x9 10

41、x 10 11 XII 12 x 12 13 x 13 14 x 14 15 x 15 16 x 16 17 x 17 18 x 18 19 x 19 20 x 20 21 x21 e = 0,65 ExD 4 x4 5x5 6x6 7 x7 8x8 9x9 10 x 10 11 XII 12 x 12 13 x 13 14 x 14 15 x 15 16 x 16 17 x 17 18 x 18 19 x 19 20 x 20 21 x21 - I - 1.20 1.30 1 .o0 1,lO 1.20 1,30 1 .o0 1.10 1.20 1,30 1 .o0 1,lO 1,20 1.

42、30 1 ,o0 1.10 1.20 1,30 rn - 1,20 1,30 1 ,o0 1,lO 1.20 1.30 1 .o0 1,lO 1,20 1,30 1 .o0 1.10 1,20 1.30 1 .o0 1,lO 1,20 I .30 nD nE n nD 4 5 7 8 9 10 12 13 14 15 17 18 19 20 22 23 24 25 - - nE 4 5 7 8 9 10 12 13 14 15 17 18 19 20 22 23 24 25 - - n 16 25 49 64 81 1 O0 144 169 196 225 289 324 361 400 48

43、4 529 576 625 - - rn - 0,80 0.90 0.60 0.70 0.80 0.90 0,60 0,70 0,80 0,90 0,60 0,70 0,80 0,90 0,60 0.70 0,80 0,90 - la - 0.80 0.90 0,60 0,70 0,80 0,90 0,60 0.70 0,80 0.90 0,60 0,70 0.80 0.90 0.60 O .70 0.80 0,90 - nD 3 4 6 7 8 9 11 12 13 14 16 17 18 19 21 22 23 24 - - nE 3 4 6 7 8 9 11 12 13 14 16 17

44、 18 19 21 22 23 24 - - n 9 16 36 49 64 81 121 144 169 196 256 289 324 361 441 4 84 529 576 - - Maximum matrix row family Maximum matrix - 1 row family Maximum matrix - 2 row family - El - 1,025 0,875 1,050 0,900 1,075 0,925 1,100 0,950 1,125 0,975 1,150 1,000 1,175 1,025 0.875 1,050 0,900 1,075 - a

45、0,700 0,550 0,725 0,575 0.750 0,600 0,775 0,625 0,800 0,650 0,825 0,675 0,850 0,700 0,550 0,725 0,575 0,750 - nD 4 6 7 9 10 12 13 15 16 18 19 21 22 24 26 27 29 30 - - nE 4 6 7 9 10 12 13 15 16 18 19 21 22 24 26 27 29 30 - - n 16 36 49 81 I O0 144 169 225 256 324 361 44 1 484 576 676 729 84 1 900 - -

46、 - 0.700 0,550 0,725 0,575 0,750 0,600 0,775 0,625 0,800 0,650 0,825 0,675 0,850 0,700 0,550 0,725 0,575 0,750 - El 1,025 0,875 1,050 0,900 1 .O75 0,925 1,100 0,950 1,125 0,975 1,150 1,000 1,175 1,025 0,875 1,050 0,900 1,075 - nD nE n nD 5 7 8 10 I1 13 14 16 17 19 20 22 23 25 27 28 30 31 - nE 5 7 8

47、10 I1 13 14 16 17 19 20 22 23 25 27 28 30 31 - n 25 49 64 1 O0 121 169 196 256 289 361 400 484 529 625 729 784 900 961 - 0 BSI 5 September 2001 11 EN 60191-6-62001 Table 5 - (continued) Maximum matrix - 2 row family Maximum matrix row family Maximum matrix - 1 row family ! = 0,50 ExD 4x4 5x5 6x6 7x7

48、 8x8 9x9 10 x 10 11 x 11 12 x 12 13 x 13 14 x 14 15 x 15 16 x 16 17 x 17 18 x 18 19 x I9 20 x 20 21 x 21 2 = 0,40 - nD 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 - - E3 - 0,75 0.75 0.75 0,75 0,75 0.75 0.75 0,75 0.75 0,75 0,75 0.75 0.75 0.75 0.75 0.75 0,75 0,75 nD 7 9 11 13 15 17 19 21 23 25

49、 27 29 31 33 35 37 39 41 - - nE 7 9 I1 13 15 17 I9 21 23 25 27 29 31 33 35 37 39 41 - - n El - 0,50 0,50 0,50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0,50 0.50 0.50 0,510 0.50 - nE n El 0.75 0,75 0.75 0,75 0,75 0.75 0.75 0,75 0.75 0.75 0.75 0.75 0.75 0,75 0,751 0,75 0,75 0.75 la 030 0,50 030 0,50 030 0,50 0.50 030 0.50 0,50 0,50 0.50 0,50 0,50 0,50 0.50 0.50 0,50 49 81 121 169 225 289 361 44 1 529 625 729 84 1 96 1 1089 1225 1369 1521 1681 - 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 - 36 64 1 O0 144 196 256 3