DLA SMD-5962-96886 REV B-2002 MICROCIRCUIT DIGITAL-LINEAR CMOS 12 BIT ANALOG TO DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS MONOLITHIC SILICON《互补金属氧化物半导体 12-BIT类似体对.pdf

《DLA SMD-5962-96886 REV B-2002 MICROCIRCUIT DIGITAL-LINEAR CMOS 12 BIT ANALOG TO DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS MONOLITHIC SILICON《互补金属氧化物半导体 12-BIT类似体对.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-96886 REV B-2002 MICROCIRCUIT DIGITAL-LINEAR CMOS 12 BIT ANALOG TO DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS MONOLITHIC SILICON《互补金属氧化物半导体 12-BIT类似体对.pdf（19页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R339-97. 97-05-20 R. MONNIN B Updated drawing to reflect current requirements. Redrawn. -rrp 02-11-18 R. MONNIN REV SHET REV B B B B SHEET 15 16 17 18 REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET

2、1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Ronald L. Couch DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Rajesh Pithadia COLUMBUS, OHIO 43216 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Raymond Monnin MICROCIRCUIT, DIGI

3、TAL-LINEAR, CMOS, 12 BIT ANALOG TO DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 96-10-14 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-96886 SHEET 1 OF 18 DSCC FORM 2233 APR 97 5962-E100-03 DIST

4、RIBUTION STATEMENT A. Approved for public release; distribution is unlimited.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96886 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHE

5、ET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identify

6、ing Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 96886 01 Q R X Federal stock class designator RHA designator (see 1.2.1) Devicetype (see 1.2.2) Device class designator Case

7、outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendi

8、x A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 TLC2543 12 bit analog to digital converters with seria

9、l control and 11 analog inputs 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class lev

10、el B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20

11、20 Dual-in-line S GDFP2-F20 or CDFP3-F20 20 Flat package 2 CQCC1-N20 20 Leadless chip carrier package 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networ

12、king permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96886 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage range, (VCC) . -0.5 V dc to +6.5 V dc 2/ Input voltage r

13、ange (VIN)(any input) . -0.3 V dc to VCC+0.3 V dc Output voltage (VOUT). -0.3 V dc to VCC+0.3 V dc Positive reference voltage, Vref+ VCC+0.1 V dc Negative reference voltage, Vref- . -0.1 V dc Peak input current (any input) . 20 mA Peak total input current (all inputs). 30 mA Storage temperature rang

14、e (TSTG) . -65C to +150C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds . +260C Thermal resistance, junction-to-case (JC). See MIL-STD-1835 1.4 Recommended operating conditions. Supply voltage (VCC) 4.5 V dc to 5.5 V dc Positive reference voltage, (Vref+) VCC3/ Negative reference volta

15、ge, (Vref-) . 0.0 V 3/ Differential reference voltage, Vref+- Vref-. +2.5 V dc to VCC+0.1 V dc 3/ Analog input voltage. 0.0 V to VCC3/ High-level control input voltage, VIH(VCC=3.0 V to 3.6 V) . 2.0 V dc Low-level control input voltage, VIL(VCC= 3.0 V to 3.6 V) . 0.8 V dc Clock frequency at I/O CLOC

16、K 0.0 MHz to 4.1 MHz Setup time, Address bits at data input before I/O CLOCK, tsu(A). 100 ns Hold time, address bits after I/O CLOCK, th(A). 0.0 ns (min) Hold time, CS low after last I/O CLOCK, th(CS)0.0 ns (min) Setup time, CS low before clocking in first address bit, tsu(CS)1.425 s 4/ Pulse durati

17、on, I/O CLOCK high, twH(I/O)120 ns (min) Pulse duration I/O CLOCK Low, twL(I/O)120 ns (min) Transition time, I/O CLOCK, tt(I/O)1 s (min) 5/ Transition time, DATA INPUT and CS , tt(CS)10 s (min) Operating free-air temperature range (TA) . -55C to +125C 1/ Stress above the absolute maximum rating may

18、cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ All voltage values are with respect to digital ground with REF- and GND wired together (unless otherwise noted). 3/ Anaolg input voltages greater than that applied to REF

19、+ convert as all ones (1111111111), while input voltages less than that applied to REF- convert as all zeros (0000000000). The device is functional with reference voltages down to V(Vref+- Vref-); However, the electrical specifications are no longer applicable. 4/ To minimize errors caused by noise

20、at CS , the internal circuitry waits for a setup time plus two falling edges of the internal system clock after CS before responding to control input signals. No attempt should be made to clock in an address until the minimum CS setup time has elapsed. 5/ This is the time required for the clock inpu

21、t signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of normal room temperature, the devices function with input clock transition time as slow as 1 s for remote data acquisition applications where the sensor and the A/D converter are placed several feet away from

22、the controlling microprocessor. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96886 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCU

23、MENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index o

24、f Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835

25、 - Interface Standard Electronic Component Case Outlines. HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the St

26、andardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supers

27、edes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality

28、Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, cons

29、truction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herei

30、n. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth tables. The truth tables shall be as specified on figure 2. 3.2.4 Block diagram. The block diagram shall be as specified on figure 3. 3.2.5 Load circuit. The load circuit shall be as specified on f

31、igure 4. 3.2.6 Timing waveforms. The timing waveforms shall be as specified on figure 5. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specifie

32、d in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. Provided by IHSNot for ResaleNo reproduction or

33、 networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96886 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test 1/ Symbol Conditions -55C TC +125C unless o

34、therwise specified Group A subgroups Device type Limits Unit Min Max IOH= -1.6 mA, VCC= 4.5 V 2.4 High-level output voltage VOHIOH= -20 A, VCC= 4.5 V to 5.5 V 1, 2, 3 01 VCC - 0.1 V IOL= 1.6 mA, VCC= 4.5 V 0.4 Low-level output voltage VOLIOL= 20 A, VCC= 4.5 V to 5.5 V 1, 2, 3 01 0.1 V IOZHCS at VCC,

35、 VOUT= VCC= 4.5 V to 5.5 V 2.5 Off-state (high-impedance state) output current IOZLCS at VCC, VOUT= 0, VCC= 4.5 V to 5.5 V 1, 2, 3 01 -2.5 A Input current high IIHVI= VCC, VCC= 4.5 V to 5.5 V 1, 2, 3 01 10.0 A Input current low IILVI= 0, VCC= 4.5 V to 5.5 V 1, 2, 3 01 -10.0 A Operating supply curren

36、t ICCCS at 0 V, VCC= 4.5 V to 5.5 V 1, 2, 3 01 10.0 mA Power-down current ICC(PD)For all digital inputs, 0 VI 0.5 V or VI VCC 0.5 V 1, 2, 3 01 25 A Selected channel at VCC, Unselected channel at 0 V, VCC= 4.5 V to 5.5 V 10 Selected channel leakage current - Selected channel at 0 V, Unselected channe

37、l at VCC, VCC= 4.5 V to 5.5 V 1, 2, 3 01 -10 A Maximum static analog reference current into REF+ - VREF+= VCC, VREF-= GND, VCC= 4.5 V to 5.5 V 1, 2, 3 01 10.0 A Analog inputs, VCC= 4.5 V to 5.5 V, See 4.4.1c 60 Input capacitance CIControl inputs, VCC= 4.5 V to 5.5 V, See 4.4.1c 4 01 15 pF Functional

38、 test See 4.4.1b 7, 8 01 Linearity error 2/ ELSee figure 5, 3/ VCC= 4.5 V to 5.5 V 4, 5, 6 01 1 LSB See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96886 DEFENSE SUPPLY CENTER C

39、OLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test 1/ Symbol Conditions -55C TC +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Differential linearity error EDSee figure 5

40、, 3/ VCC= 4.5 V to 5.5 V 4, 5, 6 01 1 LSB Offset error 4/ EOSee figure 5, 3/ VCC= 4.5 V to 5.5 V 4, 5, 6 01 1.5 LSB Gain error 4/ EGSee figure 5, 3/ VCC= 4.5 V to 5.5 V 4, 5, 6 01 1 LSB Total adjusted error 5/ ET4, 5, 6 01 1.75 LSB Conversion time tCONVSee figure 5, VCC= 4.5 V to 5.5 V 9, 10, 11 01

41、10 s Total cycle time (access, sample, and conversion) tCSee figure 5, 6/ VCC= 4.5 V to 5.5 V 9, 10, 11 01 10 + total I/O CLOCK periods + td(I/O- EOC) s Channel acquisition time (sample) tacqSee figure 5, 6/ VCC= 4.5 V to 5.5 V 9, 10, 11 01 4 12 I/O CLOCK periods Valid time, DATA OUT remains valid a

42、fter I/O CLOCK tVSee figure 5, VCC= 4.5 V to 5.5 V 9, 10, 11 01 10 ns Delay time, I/O CLOCK to DATAOUT valid td(I/O-DATA See figure 5, VCC= 4.5 V to 5.5 V 9, 10, 11 01 150 ns Delay time, last I/O CLOCK to EOC td(I/O-EOC) See figure 5, VCC= 4.5 V to 5.5 V 9, 10, 11 01 2.2 ns Delay time, EOC to DATA O

43、UT (MSB) td(EOC-DATA See figure 5, VCC= 4.5 V to 5.5 V 9, 10, 11 01 100 ns Enable time, CS to DATA OUT (MSB/LSB driven) tPZH, tPZLSee figure 5, VCC= 4.5 V to 5.5 V 9, 10, 11 01 1.3 s Disable time, CS to DATA OUT (high impedance) tPHZ, tPLZSee figure 5, VCC= 4.5 V to 5.5 V 9, 10, 11 01 150 ns Rise ti

44、me, EOC tr(EOC)See figure 5, VCC= 4.5 V to 5.5 V 9, 10, 11 01 50 ns Fall time, EOC tf(EOC)See figure 5, VCC= 4.5 V to 5.5 V 9, 10, 11 01 50 ns Rise time, data bus tr(bus)See figure 5, VCC= 4.5 V to 5.5 V 9, 10, 11 01 50 ns Fall time, data bus tf(bus)See figure 5, VCC= 4.5 V to 5.5 V 9, 10, 11 01 50

45、ns Delay time, last I/O CLOCK to CS to abort conversion td(I/O-CS) VCC= 4.5 V to 5.5 V 7/ 9, 10, 11 01 5 s See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96886 DEFENSE SUPPLY C

46、ENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. 1/ All voltage values are with respect to GND with REF- and GND wired together (unless otherwise noted). 2/ Linearity error is the maximum deviation from

47、 the best straight line through the A/D transfer characteristic. 3/ Analog input voltages greater than applied to REF+ convert as all ones (1111111111), while input voltages less than that applied to REF- convert as all zeros (0000000000). 4/ Gain error is the difference between the actual midstep v

48、alue and the nominal midstep value in the transfer diagram at the specified gain point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the nominal midstep at the offset point. 5/ Total unadjusted error comprises linearity, zero-scale, and full-scale errors. 6/ I/O CLOCK period = 1/(I/O CLOCK frequency). 7/ Any transitions of CS are recognized as valid only if the levels is maintained fo