DLA SMD-5962-95845 REV F-2013 MICROCIRCUIT MEMORY DIGITAL RADIATION-HARDENED CMOS SOI 32K X 8 STATIC RAM MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add case outline U. Add note 2/ to sheet 2. Add note 5/ to table IA. Add note 6/ to tWHWL. Make corrections to notes on sheets 11 and 13. Add note 3 to figure 3. Add note 2 to figure 5, Read Cycle. Add note 6 to figure 5, Write Cycle. Make correc

2、tion to note 5 of figure 6. Add vendor CAGE 34168 as source of supply for case outline U. Editorial corrections throughout. 97-06-12 Raymond Monnin B Corrections to sheet 16, Figure 2, Terminal Connections. - glg 01-01-05 Raymond Monnin C Change CAGE code to correct CAGE of 67268. Update boilerplate

3、. Editorial changes throughout. - gap 02-04-08 Raymond Monnin D Updated paragraph 4.4.4.2d; added paragraph 4.4.4.2e, and added paragraph 6.6.3. Corrected the S dimension for the Y package and corrected the polarity of the capacitor pads for package Z. Updated boilerplate as part of 5 year review. -

4、 ksr 09-05-18 Joseph Rodenbeck E Updated body of drawing to reflect current requirements. Added appendix B for die. - glg 11-10-18 Charles F. Saffle F Updated Figure 4 to reflect vendors current modeling and testing methods. Removed class M references. - glg 13-12-20 Charles F. Saffle REV F SHEET 35

5、 REV F F F F F F F F F F F F F F F F F F F F SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 REV STATUS REV F F F F F F F F F F F F F F OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Jeff Bowling DLA LAND AND MARITIME STANDARD MICROCIRCUIT DRAWING CHECKED BY

6、Jeff Bowling COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY All DEPARTMENTS APPROVED BY Michael. A. Frye MICROCIRCUIT, MEMORY, DIGITAL, RADIATION-HARDENED, CMOS/SOI, 32K X 8 STATIC RAM, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRA

7、WING APPROVAL DATE 96-11-26 AMSC N/A REVISION LEVEL F SIZE A CAGE CODE 67268 5962-95845 SHEET 1 OF 35 DSCC FORM 2233 APR 97 5962-E102-14 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95845 DLA LAND AND MARI

8、TIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (device class V). A choice of case outlines and lead finishes are availabl

9、e and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 H 95845 01 Q X C Federal stock class designator RHA designator (see 1.2.1) Device t

10、ype (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates

11、 a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Input/output levels Chip enable 1/ Access time 01 HX6256 32K X 8 CMOS/SOI SRAM CMOS Dual 25 ns 02 HX6256 32K X 8 CMOS/SOI SRAM TTL Dual 25 ns 03 HX6356 32

12、K X 8 CMOS/SOI SRAM CMOS Dual 25 ns 04 HX6356 32K X 8 CMOS/SOI SRAM TTL Dual 25 ns 05 HX6256 32K X 8 CMOS/SOI SRAM CMOS Dual 20 ns 06 HX6256 32K X 8 CMOS/SOI SRAM TTL Dual 20 ns 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as f

13、ollows: Device class Device requirements documentation Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X GDIP1-T28 or CDIP2-T28 28 Dual-i

14、n-line Y See figure 1 28 Flat pack Z See figure 1 36 Flat pack U See figure 1 36 Flat pack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V. _ 1/ Any device type ordered in case outlines X or Y is single chip enable. Provided by IHSNot for ResaleNo repro

15、duction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95845 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 2/ 3/ Supply voltage range (VCC) -0.5 V dc to +6.5 V dc DC input v

16、oltage range (VIN) -0.5 V dc to VCC+ 0.5 V dc DC output voltage range (VOUT) . -0.5 V dc to VCC+ 0.5 V dc Storage temperature range -65C to +150C Lead temperature (soldering, 5 seconds) +270C Thermal resistance, junction-to-case (JC): Case X . See MIL-STD-1835 Cases Y, Z, and U . 2.0C/watt Output vo

17、ltage applied to high Z state . -0.5 V dc to VCC+ 0.5 V dc Maximum power dissipation (PD) . 2 watts Maximum junction temperature (TJ) . +175C 1.4 Recommended operating conditions. Supply voltage range (VCC) 4.5 V dc (min) to 5.5 V dc (max) Supply voltage (VSS) 0.0 V dc High level input voltage range

18、 (VIH): Device type 01, 03, 05 (CMOS levels) . 0.7 x VCCto VCC+ 0.3 V dc Device type 02, 04, 06 (TTL levels) . 2.2 V dc to VCC+ 0.3 V dc Low level input voltage range (VIL): Device type 01, 03, 05 (CMOS levels) . -0.3 V dc to 0.3 x VCCDevice type 02, 04, 06 (TTL levels) . -0.3 V dc to 0.8 V dc Case

19、operating temperature range (TC) . -55C to +125C 1.5 Digital logic testing for device classes Q and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-883, method 5012) 100 percent 1.6 Radiation features. Maximum total dose available (dose rate = 50 - 300 rads(Si)/s) 106rads(Si) 2.

20、APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DE

21、PARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL

22、-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/quicksearch.dla.mil from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) _ 2/ Stresses a

23、bove the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 3/ All voltages referenced to VSS(VSS= ground), unless otherwise specified. Provided by IHSNot for ResaleNo reproduction or networking p

24、ermitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95845 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 4 DSCC FORM 2234 APR 97 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.

25、 Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM Standard F1192 - Standard Guide for the Measurement of Single Event Phenomena from Heavy Ion Irradiation of Semiconductor Devices

26、. (Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor Drive, West Conshohocken, PA 19428-2959; http:/www.astm.org.) JEDEC INTERNATIONAL (JEDEC) JESD 78 - IC Latch-Up Test. (Applications for copies should be addressed to the Electroni

27、cs Industries Association, 2500 Wilson Boulevard, Arlington, VA 22201; http:/www.jedec.org.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other

28、 informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing shall take precedence. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be

29、in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.1.1 Microcircuit die. For the requirements of microcircuit die, see app

30、endix B to this document. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein and figure 1. 3

31、.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table. The truth table shall be as specified on figure 3. 3.2.4 Output load circuit. The output load circuit shall be as specified on figure 4. 3.2.5 Radiation exposure circuit. The radiation exposure

32、circuit shall be as specified on figure 6. 3.2.6 Functional tests. Various functional tests used to test this device are contained in the appendix A. If the test patterns cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be allowed.

33、 For device classes Q and V alternate test patterns shall be under the control of the device manufacturers Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the preparing or acquiring activity upon request. 3.2.7 Die overcoat. Polyimide and silicone coatin

34、gs are allowable as an overcoat on the die for alpha particle protection only. Each coated microcircuit inspection lot (see inspection lot as defined in MIL-PRF-38535) shall be subjected to and pass the internal moisture content test at 5000 ppm (see method 1018 of MIL-STD-883). The TRB will ascerta

35、in the requirements as provided by MIL-PRF-38535 for classes Q and V. Samples may be pulled any time after seal. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation paramete

36、r limits are as specified in table IA and shall apply over the full case operating temperature range. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95845 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVI

37、SION LEVEL F SHEET 5 DSCC FORM 2234 APR 97 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In add

38、ition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Ma

39、rking for device classes Q and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. 3.6 Certificate of compliance. For device classes Q and V, a certificate of complia

40、nce shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufactur

41、ers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from

42、 IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95845 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 6 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics. Test Symbol Conditions -55C TC+125C 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups D

43、evice Type Limits Unit Min Max High level output voltage VOHVCC= 4.5 V, IOH= -5 mA, VIL= 1.35 V, VIH= 3.15 V 1, 2, 3 01,03,05 4.2 V VCC= 4.5 V, IOH= -4 mA, VIL= 0.8 V, VIH= 2.2 V 02,04,06 4.2 M,D,L,P,R,F,G,H 1 1/ 2/ Low level output voltage VOLVCC= 4.5 V, IOL= 10 mA, VIL= 1.35 V, VIH= 3.15 V 1, 2, 3

44、 01,03,05 0.4 V VCC= 4.5 V, IOL= 8 mA, VIL= 0.8 V, VIH= 2.2 V 02,04,06 0.4 M,D,L,P,R,F,G,H 1 1/ 2/ Input leakage current IILKVIN= 0.0 V to 5.5 V, all other pins at 0.0 V, VCC= 5.5 V 1, 2, 3 All -5 5 A M,D,L,P,R,F,G,H 1 1/ 2/ 2/ Output leakage current IOLKVOUT= 0.0 V to 5.5 V, all other pins at 0.0 V

45、, VCC= 5.5 V 1, 2, 3 All -10 10 A M,D,L,P,R,F,G,H 1 1/ 2/ 2/ Data retention voltage VDRVCC= 2.5 V 1, 2, 3 All 2.5 A M,D,L,P,R,F,G,H 1 1/ 2/ Operating supply current ICC1VCC= 5.5 V, no output loading S = GND, E = VCC4/, 1, 2, 3 All 160 mA f = fMAX3/, M,D,L,P,R,F,G,H 1 1/ 2/ Supply current (deselected

46、) ICC2VCC= 5.5 V, f = fMAX3/ S = VCC, E = GND 4/ 1, 2, 3 All 1.5 mA M,D,L,P,R,F,G,H 1 1/ 2/ Supply current (standby) ICC3VCC= 5.5 V, f = 0 Mhz, S = VCC, E = GND 1, 2, 3 All 1.5 mA M,D,L,P,R,F,G,H 1 1/ 2/ Data retention current ICC4VCC= 2.5 V 1, 2, 3 01,02,05,06 500 A VCC= 3.0 V 03,04 330 M,D,L,P,R,F

47、,G,H 1 1/ 2/ See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95845 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 7 DSCC FORM 2234 APR 97 TABLE IA. Elect

48、rical performance characteristics - continued. Test Symbol Conditions -55C TC+125C 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device Type Limits Unit Min Max Input capacitance 5/ CINVI= 5.0 V or 0.0 V, f = 1 Mhz TA= +25C, see 4.4.1d 4 All 7 pF Output capacitance 5/ COUTVO= 5.0 V or 0.0 V, f = 1 Mhz TA= +25C, see 4.4.1d 4 All 9 pF Functional tests See 4.4.1c 7, 8A, 8B All M,D,L,P,R,F,G,H 7 1/ 2/ Read cycle time tAVAVSee figures 4 and 5