DLA SMD-5962-91603 REV B-2008 MICROCIRCUIT DIGITAL ADVANCED CMOS 4-STAGE SYNCHRONOUS BIDIRECTIONAL COUNTER MONOLITHIC SILICON《单片硅四态同步双向计数器 改进的CMOS数字微电路》.pdf
《DLA SMD-5962-91603 REV B-2008 MICROCIRCUIT DIGITAL ADVANCED CMOS 4-STAGE SYNCHRONOUS BIDIRECTIONAL COUNTER MONOLITHIC SILICON《单片硅四态同步双向计数器 改进的CMOS数字微电路》.pdf》由会员分享,可在线阅读,更多相关《DLA SMD-5962-91603 REV B-2008 MICROCIRCUIT DIGITAL ADVANCED CMOS 4-STAGE SYNCHRONOUS BIDIRECTIONAL COUNTER MONOLITHIC SILICON《单片硅四态同步双向计数器 改进的CMOS数字微电路》.pdf(20页珍藏版)》请在麦多课文档分享上搜索。
1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add device class V criteria. Add RHA data. Editorial changes throughout.- jak 98-02-04 Thomas M. Hess B Update boilerplate to MIL-PRF-38535 requirements. - LTG 08-07-24 Thomas M. Hess REV SHET REV B B B B B SHEET 15 16 17 18 19 REV STATUS REV B B
2、 B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Marcia B. Kelleher CHECKED BY Monica L. Poelking DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil APPROVED BY Michael A. Frye STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AV
3、AILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 92-04-09 MICROCIRCUIT, DIGITAL, ADVANCED CMOS, 4-STAGE SYNCHRONOUS BIDIRECTIONAL COUNTER, MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-91603 SHEET 1 OF 19 DSCC FORM 2233 APR
4、 97 5962-E468-08 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91603 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing
5、documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hard
6、ness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 R 91603 01 V E A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / D
7、rawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate
8、RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54AC169 4-stage synchronous bidirectional counter 1.2.3 Device class designator. The device class designator is a s
9、ingle letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualifi
10、cation to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line F GDFP2-F16 or CDFP3-F16 16 Flat pack 2 CQCC1-N20 20 Square leadless chip carrie
11、r 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91603 DEFENSE
12、SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VCC) -0.5 V dc to +6.0 V dc DC input voltage range (VIN) -0.5 V dc to VCC + 0.5 V dc DC output voltage range (VOUT) . -0.5 V dc to VCC+ 0.5 V d
13、c Clamp diode current. 20 mA DC output current (per pin) 50 mA DC VCCor GND current (per pin) . 50 mA Maximum power dissipation (PD) . 500 mW Storage temperature range (TSTG) . -65C to +150C Lead temperature (soldering, 10 seconds). +300C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835
14、Junction temperature (TJ) +175C 4/ 1.4 Recommended operating conditions. 2/ 3/ 5/ Supply voltage range (VCC) 3.0 V dc to +5.5 V dc Input voltage range (VIN) +0.0 V dc to VCCOutput voltage range (VOUT). +0.0 V dc to VCCCase operating temperature range (TC). -55C to +125C Input rise or fall times: VCC
15、= 3.6 V to 5.5 V . 0 to 8 ns/V Minimum setup time, Pn to CP (ts1): TC= +25C, VCC= 3.0 V. 6.0 ns TC= +25C, VCC= 4.5 V. 3.5 ns TC= -55C and +125C, VCC = 3.0 V. 7.0 ns TC= -55C and +125C, VCC= 4.5 V. 4.5 ns Minimum hold time, Pn to CP (th1): TC= +25C, VCC = 3.0 V 1.0 ns TC= +25C, VCC = 4.5 V 2.5 ns TC=
16、 -55C and +125C, VCC= 3.0 V 2.0 ns TC= -55C and +125C, VCC= 4.5 V 2.5 ns Minimum setup time, CEP to CP (ts2): TC= +25C, VCC = 3.0 V 10.5 ns TC= +25C, VCC = 4.5 V 7.5 ns TC= -55C and +125C, VCC= 3.0 V13.5 ns TC= -55C and +125C, VCC= 4.5 V 9.0 ns Minimum hold time, CEP to CP (th2): TC= +25C, VCC = 3.0
17、 V 0.0 ns TC= +25C, VCC = 4.5 V 1.5 ns TC= -55C and +125C, VCC= 3.0 V 0.5 ns TC= -55C and +125C, VCC= 4.5 V 2.5 ns Minimum setup time, CET to CP (tS3): TC= +25C, VCC = 3.0 V 10.5 ns TC= +25C, VCC = 4.5 V 7.5 ns TC= -55C and +125C, VCC= 3.0 V13.5 ns TC= -55C and +125C, VCC= 4.5 V 9.0 ns 1/ Stresses a
18、bove the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise noted, all voltages are referenced to GND. 3/ The limits for the parameters specified herein shall apply over the fu
19、ll specified VCCrange and case temperature range of -55C to +125C. 4/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. 5/ Operation from 2.0 V dc to 3.0 V dc is provided for compatibilit
20、y with data retention and battery back-up systems. Data retention implies no input transition and no stored data loss with the following conditions: VIH 70% VCC, VIL 30% VCC, VOH 70% VCCat -20 A, VOL 30% VCCat 20 A. Provided by IHSNot for ResaleNo reproduction or networking permitted without license
21、 from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91603 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions Continued. Minimum hold time, CET to CP (th3): TC= +25C, VCC = 3.0 V. 0.0 ns TC= +25C, VCC = 4.5
22、V. 1.5 ns TC= -55C and +125C, VCC= 3.0 V 0.5 ns TC= -55C and +125C, VCC= 4.5 V 2.5 ns Minimum pulse width CP (tw): TC= +25C, VCC = 3.0 V. 5.0 ns TC= +25C, VCC = 4.5 V. 5.0 ns TC= -55C and +125C, VCC= 3.0 V 5.0 ns TC= -55C and +125C, VCC= 4.5 V 5.0 ns Minimum setup time, PE to CP (ts4): TC= +25C, VCC
23、 = 3.0 V. 7.0 ns TC= +25C, VCC = 4.5 V. 5.0 ns TC= -55C and +125C, VCC= 3.0 V 8.5 ns TC= -55C and +125C, VCC= 4.5 V 6.5 ns Minimum hold time, PE to CP (th4): TC= +25C, VCC = 3.0 V. 0.0 ns TC= +25C, VCC = 4.5 V. 1.5 ns TC= -55C and +125C, VCC= 3.0 V 0.5 ns TC= -55C and +125C, VCC= 4.5 V 2.0 ns Minimu
24、m setup time, U/D to CP (ts5): TC= +25C, VCC = 3.0 V.10.0 ns TC= +25C, VCC = 4.5 V. 7.5 ns TC= -55C and +125C, VCC= 3.0 V 13.0 ns TC= -55C and +125C, VCC= 4.5 V 9.0 ns Minimum hold time, U/D to CP (th5): TC= +25C, VCC = 3.0 V. 0.0 ns TC= +25C, VCC = 4.5 V. 1.5 ns TC= -55C and +125C, VCC= 3.0 V 0.5 n
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