DLA SMD-5962-89735 REV F-2013 MICROCIRCUIT DIGITAL ADVANCED CMOS OCTAL D-TYPE FLIP-FLOP WITH RESET TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf
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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Technical and editorial changes throughout. 92-04-17 M. L. Poelking B Change boilerplate to add QML class V criteria. Add ground bounce immunity characterization. Editorial changes throughout. 97-05-15 T.M. Hess C Add RHA limits - jak. 98-05-29 M
2、onica L. Poelking D Make corrections to figure 5. Update boilerplate. - jak 00-08-16 Monica L. Poelking E Update the boilerplate to current MIL-PRF-38535 requirements. Update radiation hardness assurance requirements. - jak 08-03-17 Thomas M. Hess F Correct typo “maximum” to “minimum “ hold time, pu
3、lse width time and removal time to section 1.4. Update test condition for high and low level output voltage (VOH,VOL) to table I. Update the boilerplate paragraphs to current MIL-PRF-38535 requirements. - MAA 13-11-14 Thomas M. Hess REV SHEET REV F F F F F F SHEET 15 16 17 18 19 20 REV STATUS REV F
4、F F F F F F F F F F F F F OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY James E. Nicklaus DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Thomas J. Ricciuti THIS DRAWING IS AVAILABLE FOR USE BY ALL DEP
5、ARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE APPROVED BY Michael A. Frye MICROCIRCUIT, DIGITAL, ADVANCED CMOS, OCTAL D-TYPE FLIP-FLOP WITH RESET, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON DRAWING APPROVAL DATE 90-10-02 AMSC N/A REVISION LEVEL F SIZE A CAGE CODE 67268 5962-89735 SHEET 1 OF 20 D
6、SCC FORM 2233 APR 97 5962-E029-14 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89735 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 2 DSCC FORM 2233 APR 97 1. SCOPE 1.1 Scope. This
7、drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiat
8、ion Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following examples: For device classes M and Q: 5962 - 89735 01 R A Federal RHA Device Case Lead stock class designator type outline finish designator (see 1.2.1) (see 1.2.2) (see 1.2.4) (see 1.2.5) / /
9、Drawing number For device class V: 5962 R 89735 01 V R A Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked d
10、evices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device typ
11、e(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54ACTQ273 Octal D type flip-flop with reset, TTL compatible inputs 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level a
12、s listed below. Since the device class designator has been added after the original issuance of this drawing, device classes M and Q designators will not be included in the PIN and will not be marked on the device. Device class Device requirements documentation M Vendor self-certification to the req
13、uirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWIN
14、G SIZE A 5962-89735 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 3 DSCC FORM 2233 APR 97 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20 Du
15、al-in-line S GDFP2-F20 or CDFP3-F20 20 Flat pack 2 CQCC1-N20 20 Square leadless chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VC
16、C) -0.5 V dc to +6.0 V dc DC input voltage range (VIN) -0.5 V dc to VCC + 0.5 V dc DC output voltage range (VOUT) . -0.5 V dc to VCC+ 0.5 V dc DC input diode current . 20 mA DC output diode current (per output pin) . 50 mA DC output source or sink current (per output pin) 50 mA DC VCCor GND current
17、. 100 mA Storage temperature range -65C to +150C Maximum power dissipation (PD) 500 mW Lead temperature (soldering, 10 seconds) +300C Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Junction temperature (TJ) +175C 4/ 1.4 Recommended operating conditions. 2/ 3/ Supply voltage range (VCC) +
18、4.5 V dc to +5.5 V dc Input voltage range (VIN) +0.0 V dc to VCCOutput voltage range (VOUT) +0.0 V dc to VCCCase operating temperature range (TC) . -55C to +125C Maximum Input rise or fall rate (t/v) 8 ns/V Minimum high level input voltage (IOH) . -24 mA Maximum low level output current (IOL) . +24
19、mA Maximum frequency, (fmax): TC= +25C: VCC= 4.5 V to 5.5 V 95 MHz TC= -55C, +125C: VCC= 4.5 V to 5.5 V 85 MHz Minimum setup time, Dn to CP (ts): TC= +25C: VCC= 4.5 V to 5.5 V 5.0 ns TC= -55C, +125C: VCC= 4.5 V to 5.5 V 5.0 ns Provided by IHSNot for ResaleNo reproduction or networking permitted with
20、out license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89735 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 4 DSCC FORM 2233 APR 97 Minimum hold time, Dn to CP (th): TC= +25: VCC= 4.5 V to 5.5 V 2.0 ns TC= -55C, +125C: VCC= 4.5 V to 5.5 V 2.0 ns Minimum clock high
21、, low pulse width (tw1): TC= +25C: VCC= 4.5 V to 5.5 V 5.0 ns TC= -55C, +125C: VCC= 4.5 V to 5.5 V 5.0 ns Minimum pulse width, MR low (tw2): TC= +25: VCC= 4.5 V to 5.5 V 5.0 ns TC= -55C, +125C: VCC= 4.5 V to 5.5 V 5.0 ns Minimum removal time, MR to clock (trem): TC= +25: VCC= 4.5 V to 5.5 V 4.0 ns T
22、C= -55C, +125C: VCC= 4.5 V to 5.5 V 4.0 ns 1.5 Radiation features. Maximum total dose available (dose rate = 50 300 rads (Si)/s) . 100 krads (Si) 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance a
23、nd affect reliability. 2/ Unless otherwise noted, all voltages are referenced to GND. 3/ The limits for the parameters specified herein shall apply over the full specified VCCrange and case temperature range of -55C to +125C. 4/ Maximum junction temperature shall not be exceeded except for allowable
24、 short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89735 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL
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