DLA SMD-5962-89525 REV C-2012 MICROCIRCUIT DIGITAL BIPOLAR ADVANCED SCHOTTKY TTL BUS INTERFACE FLIP-FLOP MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R011-96. ltg 95-11-29 Monica L. Poelking B Update to reflect latest changes in format and requirements. Editorial changes throughout. -les 04-08-05 Raymond Monnin C Update drawing as part of 5 year review. -jt

2、12-01-19 C. SAFFLE THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV SHEET REV STATUS REV C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Christopher A. Rauch DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDA

3、RD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Raymond Monnin APPROVED BY Michael A. Frye MICROCIRCUIT, DIGITAL, BIPOLAR, ADVANCED SCHOTTKY, TTL, BUS INTERFACE FLIP-FLOP, MONOLITHIC SILICON DRAWING APPROVAL DATE 89-02

4、-16 AMSC N/A REVISION LEVEL C SIZE A CAGE CODE 67268 5962-89525 SHEET 1 OF 10 DSCC FORM 2233 APR 97 5962-E129-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89525 DLA LAND AND MARITIME COLUMBUS, OHIO 4321

5、8-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the

6、following example: 5962-89525 01 L A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device types. The device type identify the circuit function as follows: Device type Generic number Circuit function 01 54AS823A Bus interface flip-flop with three-state

7、output 1.2.2 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style L GDIP3-T24 or CDIP4-T24 24 dual-in-line K GDFP2-F24 or CDFP3-F24 24 flat 3 CQCC1-N28 28 square chip carrier 1.2.3 Lead finish. The lead finis

8、h is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range . -0.5 V dc minimum to +7.0 V dc maximum Input voltage range . -1.2 V dc at 18 mA to +7.0 V dc Voltage applied to a disabled three-state output . 5.5 V Storage temperature range -65C to +150C Maximum p

9、ower dissipation (PD) . 566.5 mW 1/ Lead temperature (soldering, 10 seconds) +300C Junction temperature (TJ) +175C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 1.4 Recommended operating conditions. Supply voltage range (VCC) +4.5 V dc minimum to +5.5 V dc maximum Minimum high level i

10、nput voltage (VIH) . 2.0 V dc Maximum low level input voltage (VIL) 0.8 V dc Maximum high level output Current (IOH) -24 mA Maximum low level output current (IOL) 32 mA Case operating temperature range (TC) . -55C to +125C Minimum pulse duration (tw): CLR low 7.5 ns CLK high or low 9.5 ns _ 1/ Maxim

11、um power dissipation is defined as VCCX ICC, and must withstand the added PDdue to short circuit test e.g., IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89525 DLA LAND AND MARITIME COLUMBUS, OHIO 4321

12、8-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions - Continued. Minimum setup time before CLK (tsu): CLR inactive 8 ns Data 7 ns CLKEN high or low 10.5 ns Minimum hold time (th): CLKEN or data after CLK 0 ns 2. APPLICABLE DOCUMENTS 2.1 Government specification

13、, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 -

14、 Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawing

15、s. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conf

16、lict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item re

17、quirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitiona

18、l certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements he

19、rein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. Provided by IHSNot for Resal

20、eNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89525 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 3.2 Design, construction, and physical dimensions. The design, construction, and physic

21、al dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specifi

22、ed on figure 2. 3.2.4 Test circuit and switching waveforms. The test circuit and switching waveforms shall be as specified on figure 3. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall appl

23、y over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix

24、 A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Cer

25、tification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option

26、is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved sourc

27、e of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to

28、 this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritime s agent, and the acquiring activity retain the option to review the man

29、ufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89525 DLA LAND

30、AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C 1/ unless otherwise specified Group A subgroups Device type Limits Unit Min Max High level output voltage VOHVCC= 4.5 V, VIH= 2.

31、0 V, VIL= 0.8 V 2/ IOH= -2.0 mA 1, 2, 3 All 2.5 V IOH= -15 mA 1, 2, 3 All 2.4 V IOH= -24 mA 1, 2, 3 All 2.0 V Low level output voltage VOLIOL= 32 mA 1, 2, 3 All 0.5 V Input clamp voltage VICVCC= 4.5 V, IIN= -18 mA 1, 2, 3 All -1.2 V High level input current IIH1VCC= 5.5 V, VIN= 2.7 V, All other inpu

32、ts = 0.0 V 1, 2, 3 All 20 A IIH2VCC= 5.5 V, VIN= 7.0 V, All other inputs = 0.0 V 1, 2, 3 All 0.1 mA Low level input current IILVCC= 5.5 V, VIN= 0.4 V, All other inputs = 4.5 V 1, 2, 3 All -0.5 mA Output current IOVCC= 5.5 V, VOUT= 2.25 V 3/ 1, 2, 3 All -30 -112 mA Off state output current IOZHVCC= 5

33、.5 V, VOUT= 2.7 V 1, 2, 3 All 50 A IOZLVCC= 5.5 V, VOUT= 0.4 V 1, 2, 3 All -50 A Supply current ICCVCC= 5.5 V Outputs high 1, 2, 3 All 80 mA Outputs low 1, 2, 3 All 100 mA Outputs disabled 1, 2, 3 All 103 mA Functional tests See 4.3.1c 7, 8 All Propagation delay time, tPLH1VCC= 4.5 V to 5.5 V 9, 10,

34、 11 All 3.5 9.0 ns CLK to any Q tPHL1 RL= 500 9, 10, 11 All 3.5 14.0 ns Propagation delay time, CLR to any Q tPHL2 CL= 50 pF see figure 3 4/ 9, 10, 11 All 3.5 16.5 ns Output enable time, tPZH9, 10, 11 All 4.0 12.0 ns OC to any Q tPZL 9, 10, 11 All 4.0 13.0 ns Output disable time, tPHZ, 9, 10, 11 All

35、 1.0 10.0 ns OC to any Q tPLZ 1/ Unused inputs that do not directly control the pin under test must be 2.5 V or 0.4 V. No unused inputs shall exceed 5.5 V or go less than 0.0 V. No inputs shall be floated. 2/ All outputs must be tested. In the case where only one input at VILmaximum or VIHminimum pr

36、oduces the proper output state, the test must be performed with each input being selected as the VILmaximum or VIHminimum input. 3/ The output conditions have been chosen to produce a current that closely approximates one-half of the true short circuit output current, IOS. Not more than one output w

37、ill be tested at one time and the duration of the test condition shall not exceed one second. 4/ Propagation delay limits are based on single output switching. Unused inputs = 3.5 V or 0.3 V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD M

38、ICROCIRCUIT DRAWING SIZE A 5962-89525 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 Device type 01 Case outlines K and L 3 Terminal number Terminal symbol 1 OC NC 2 1D OC 3 2D 1D 4 3D 2D 5 4D 3D 6 5D 4D 7 6D 5D 8 7D NC 9 8D 6D 10 9D 7D 11 CLR 8D 12 GN

39、D 9D 13 CLK CLR 14 CLKEN GND 15 9Q NC 16 8Q CLK 17 7Q CLKEN 18 6Q 9Q 19 5Q 8Q 20 4Q 7Q 21 3Q 6Q 22 2Q NC 23 1Q 5Q 24 VCC4Q 25 - - - 3Q 26 - - - 2Q 27 - - - 1Q 28 - - - VCCFIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,

40、-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89525 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 Inputs Output OC CLR CLKEN CLK D Q L L X X X L L H L H H L H L L L L H H X X Q0 H X X X X Z H = High voltage level L = Low voltage level Z = High impedance

41、X = Irrelevant = Transition from low to high level Q0= Original level of Q before input conditions established FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89525 DLA LAND AND MARITIM

42、E COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 8 DSCC FORM 2234 APR 97 NOTES: 1. CLincludes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditi

43、ons such that the output is high except when disabled by the output control. 3. All input pulses have the following characteristics: PRR 10 MHz, duty cycle = 50%, tr= tf= 3 ns 1 ns. 4. When measuring propagation delay times of three-state outputs, switch 1 is open. 5. The outputs are measured one at

44、 a time with one input transition per measurement. FIGURE 3. Test circuit and switching waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89525 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISIO

45、N LEVEL C SHEET 9 DSCC FORM 2234 APR 97 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior

46、to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acq

47、uiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in tabl

48、e II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. TABLE II. Electrical test requirements. MIL-STD-883 test requirements Subgroups (in accordance with MIL-STD-883, method 5005, table I) Interim electrical parameters (method 5004) - - - Final electrical test parameters (method 5004) 1*, 2, 3, 7, 8, 9, 10, 11 Group A test requirements (method 5005) 1, 2, 3, 7, 8, 9, 10, 11 Groups C and D end-point electr