DLA SMD-5962-89519 REV F-1998 MICROCIRCUIT DIGITAL CMOS 16-BIT MICROPROCESSOR MIL-STD-1750 INSTRUCTION SET ARCHITECTURE MONOLITHIC SILICON《硅单片MIL-STD-1750型指令集架构16位微处理器互补型金属氧化物半导体线性.pdf

《DLA SMD-5962-89519 REV F-1998 MICROCIRCUIT DIGITAL CMOS 16-BIT MICROPROCESSOR MIL-STD-1750 INSTRUCTION SET ARCHITECTURE MONOLITHIC SILICON《硅单片MIL-STD-1750型指令集架构16位微处理器互补型金属氧化物半导体线性.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-89519 REV F-1998 MICROCIRCUIT DIGITAL CMOS 16-BIT MICROPROCESSOR MIL-STD-1750 INSTRUCTION SET ARCHITECTURE MONOLITHIC SILICON《硅单片MIL-STD-1750型指令集架构16位微处理器互补型金属氧化物半导体线性.pdf（38页珍藏版）》请在麦多课文档分享上搜索。

1、REVISIONS LTR A DESCRIPTION DATE (YR-MO-DA) APPROVED Technical changes to 1.2.2 and 1.4. Technical changes in table I. Adjustment to figure 4. Editorial changes throughout. 90-08-1 5 William K. Heckman B D E F Add device types 02, 03, 92, and 93. Update boilerplate to full OPOPN SMD. Editorial chang

2、es throughout. I I 93-03-1 7 Monica L. Poelking Changes in accordance with NOR 5962-R138-94 94-03-28 Monica L. Poelking Changes in accordance with NOR 5962-R182-96 96-09-1 2 Monica L. Poelking Add device types 04 and 05. Update boilerplate. Editorial changes throughout. - 98-1 0-23 Monica L. Poelkin

3、g tvn C I Changes in accordance with NOR 5962-R190-93 I 93-06-23 I Monica L. Poelking SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 REV SHEET REV STATUS OF SHEETS PMIC N/A FFFFFFFFFFFFFF 12 3 4 5 6 7 8 9 1011121314 STAN DARD MICROCIRCUIT DRAWING AND AGENCIES OF THE THIS DRAWING I

4、S AVAILABLE FOR USE BY ALL DEPARTMENTS ! PREPAREDBY Tim H. Noh CHECKED BY Tim H. Noh DEPARTMENT OF DEFENSE AMSC N/A DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216 REVISION LEVEL F APPROVEDBY William K. Heckman DRAWING APPROVAL DATE 89-02-1 5 MICROCIRCUIT, DIGITAL, CMOS, 16-BIT MICROPROCESSOR, M

5、IL-STD-1750 INSTRUCTION SET ARCHITECTURE, MONOLITHIC SILICON 5962-8951 9 SIZE CAGE CODE A I 67268 I SHEET 1 OF 37 DSCC FORM 2233 APR 97 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited 5962-E406-98 Provided by IHSNot for ResaleNo reproduction or networking permitted w

6、ithout license from IHS-,-,-1. SCOPE 1 .I Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identi

7、fying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 m. The PIN is as shown in the following example: o1 5962 8951 9 - * * * * * * M - * * X - * * X - * * * * * * * * Federal RHA Device Device Case Lead stock class designator type cl

8、ass outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) V Drawing number 1.2.1 RHA desiqnator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA m

9、arked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type I/ Frequency z/ Scale=O Scale=l o1 40 MHz 20

10、 MHz 02 33MHz 16MHz 03 _ 40 MHz 04 _ 40 MHz 05 _ 40 MHz 91 40 MHz 20 MHz - 92 33MHz 16MHz 93 _ 40 MHz Generic number BXI 750A (see 6.6) BXI 750A (see 6.6) BXI 750A (see 6.6) BXI 750A-3D (see 6.6) BXI 750A-3D (see 6.6) BXI 750A (see 6.6) BXI 750A (see 6.6) BXI 750A (see 6.6) Circuit function 16-bit m

11、icroprocessor with MIL-STD-I 750 instruction set architecture, full terminal connection 16-bit microprocessor with MIL-STD-I 750 instruction set architecture, full terminal connection 16-bit microprocessor with MIL-STD-I 750 instruction set architecture, full terminal connection 16-bit microprocesso

12、r with MIL-STD-I 750 instruction set architecture, full terminal connection 16-bit microprocessor with MIL-STD-I 750 instruction set architecture, full terminal connection 16-bit microprocessor with MIL-STD-I 750 instruction set architecture, reduced terminal connection (see figure 2) 16-bit micropr

13、ocessor with MIL-STD-I 750 instruction set architecture, reduced terminal connection (see figure 2) 16-bit microprocessor with MIL-STD-I 750 instruction set architecture, reduced terminal connection (see figure 2) - I/ Device types 04 and 05 must be fabricated using 1.2 pm technology. - 21 Values wi

14、th Scale = 1 are for SCLK = 2 FCLK periods, Scale = O are for SCLK = 4 FCLK periods (see 6.5) STAN DARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 I 5962-89519 I SHEET2 REVISION LEVEL F ISCC FORM 2234 APR 97 Provided by IHSNot for ResaleNo reproduction or networkin

15、g permitted without license from IHS-,-,-1.2.3 Device class desiqnator. The device class designator is a single letter identifying the product assurance level as fol lows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JA

16、N class level B microcircuits in accordance with MIL-PRF-38535, appendix A QorV Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-I835 and as follows: Outline letter Descriptive desiqnator Terminals Packaqe style X CMGAI 7-PI 21

17、121 Pin grid array Y See figure 1 1 O0 Leaded chip carrier with gullwing-leads Z CMGAI 7-PI 13 113 Pin grid array U CMGA5-PI 21 121 Pin grid array T CMGA5-PI 13 113 Pin grid array 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendi

18、x A for device class M. 1.3 Absolute maximum ratinqs. I/ Supply voltage range (VDD) -0.7 V dc to +7.0 V dc Input voltage range (VIN) -0.7 V dc to +7.0 V dc Storage temperature range (Tsc) -65C to +150C Lead temperature (soldering, 1 O seconds) . +300C Thermal resistance, junction-to-case (OJC): Case

19、 X, Z, U, and T Case Y I O“C/W Junction temperature (TJ) +I 65C Maximum power dissipation (PD) . 1 .4 W See MIL-STD-I835 1.4 Recommended operatinq conditions. Supply voltage range (VDD) +4.5 V dc to +5.5 V dc Minimum high level input voltage: FCLK . VDD - 0.5 V dc RESETB, INTOB - INT7B, PWRDNB, FTSP

20、ARE, PIOXEB, PEB, BITE, MPROEB, ILLADDB . 2.8 V dc FTSPARE, PIOXEB, PEB, BITE, MPROEB, ILLADDB 2.4 V dc FCLK . 0.5 V dc Excluding FCLK . 0.8 V dc Device types O1 and 91 . 20 MHz Device types 02 and 92 . 16 MHz Device types 03, 04, 05, and 93 . 40 MHz Excluding FCLK, RESETB, INTOB - INT7B, PWRDNB, Ma

21、ximum low level input voltage: Operating frequency (FCLK): z/ - I/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. - 21 Values represented are with Scale = 1 (SCLK = 2 FCLK p

22、eriods). If Scale = O then frequency would approximtely double (see 6.5). STAN DARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 I 5962-89519 I SHEET3 REVISION LEVEL F ISCC FORM 2234 APR 97 Provided by IHSNot for ResaleNo reproduction or networking permitted without

23、license from IHS-,-,-Case operating temperature range (TC): Device types 01, 02, 03, 91, 92, and 93 . -55C to +125“C Device type 04 . -55C to +95“C Device type 05 . -55C to +I 05C 1.5 Diqital loqic testinq for device classes Q and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-8

24、83, test method 5012) 91 percent 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those liste

25、d in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENTOFDEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENTOFDEFENSE MIL-STD-883 - T

26、est Methods and Procedures for Microelectronics. MIL-STD-973 - Configuration Management. MIL-STD-I 835 - Interface Standard For Microcircuit Case Outlines. MIL-STD-I 750 - Airborne Computer Instruction Set Architecture. HANDBOOKS DEPARTMENTOFDEFENSE MIL-HDBK-I 03 - MIL-HDBK-780 - Standard Microcircu

27、it Drawings. List of Standard Microcircuit Drawings (SMDs). (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 191 11 -5094.) 2.2 Order of precedence. In the

28、event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The ind

29、ividual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individ

30、ual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. STAN DARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 I 5962-89519 I SHEET4 REVISION LEVEL F ISCC FORM 2234 APR

31、97 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-3.2 Desiqn, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, app

32、endix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 and figure 1 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Functional block diaqram. The functional block diagram shall be as specif

33、ied on figure 3. 3.2.4 Timinq waveforms. The timimg waveforms shall be as specified on figure 4. 3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be as specified when available. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise sp

34、ecified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II.

35、 The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to spa

36、ce limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with

37、MIL-PRF-38535, appendix A. 3.5.1 Certificationkompliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For de

38、vice classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approv

39、ed source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF- 38535 and herein or

40、 for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits deli

41、vered to this drawing. 3.8 Certification. Certification to MIL-STD-I 750 verification software (VSW) test shall be required and the manufacturer shall be listed on the Air Force VSW compliant computer list. 3.9 Notification of chanqe for device class M. For device class M, notification to DSCC-VA of

42、 change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change as defined in MIL-STD-973. 3.10 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facili

43、ty and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.1 1 Microcircuit qroup assiqnment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 105 (see MIL-PRF-38535, appendi

44、x A). STAN DARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 I 5962-89519 I SHEET5 REVISION LEVEL F ISCC FORM 2234 APR 97 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-TABLE I. Electrical performance characteristics

45、. Symbol Test Test conditions 11 unless otherwise specified +4.5 v # vDD # +5.5 VOH Input voltage low excluding Input voltage low for FCLK FCLK and SCANEN and SCANEN VDD = 4.5 V, IOH = -8 mA VDD = 4.5 V, IOH = -500 : A Input voltage high excluding FCLK, RESETB, SCANEN, PWRDNB, FTSPARE, PIOXEB, BITE,

46、 MPROEB. ILLADDB INTOB-INT7B, PEB, VIHS Input voltage high for FCLK Input voltage high for RESETB, INTOB-INT7B, PEB, SCANEN, PWRDNB, FTSPARE, PIOXEB, BITE, MPROEB, ILLADDB VIHC VIHR Output voltage low excluding SCLK and data bus Output voltage low for SCLK Output voltage low for data bus i VDD = 4.5

47、 V, IOL = 7 mA VDD = 4.5 V, IOL = 5 mA Output voltage high excluding SCLK Output voltage high for SCLK I I Vnn = 4.5 V. hH = -500 : A Input current low excluding Input current low for TSB 21 TSB 21 iILT I vDD = 5.5 v. vIN = GND Input current high 21 I IIH I vDD = 5.5 V, VIN = 5.5 v See footnotes at

48、end of table. Unit V :A STAN DARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 I 5962-89519 I SHEET6 REVISION LEVEL F ISCC FORM 2234 APR 97 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-TABLE I. Electrical performan

49、ce characteristics - Continued. Test Symbol Test conditions 11 unless otherwise specified +4.5 v # vDD # +5.5 Device type IOZH VDD = 5.5 V, Vo = 5.5 v Three-state output current high 21 Three-state output current low excluding DATA 21 All All IOZL VDD = 5.5 V, Vo = 0.5 V Three-state output current low for DATA 21 OZLD 01, 02, 03, 91, 92. 93 VDD = 5.5 V, Vo = 0.0 V 31 VDD = 5.5 V 04, 05 03, 91, 92, 93 01, 02, Static VDD supply current IDD 04.