DLA SMD-5962-89518 REV A-2002 MICROCIRCUIT LINEAR CMOS 8-BIT A D CONVERTER WITH TRACK HOLD MONOLITHIC SILICON《硅单片A D转换跑道 搁置8位互补型金属氧化物半导体线性微电路》.pdf

《DLA SMD-5962-89518 REV A-2002 MICROCIRCUIT LINEAR CMOS 8-BIT A D CONVERTER WITH TRACK HOLD MONOLITHIC SILICON《硅单片A D转换跑道 搁置8位互补型金属氧化物半导体线性微电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-89518 REV A-2002 MICROCIRCUIT LINEAR CMOS 8-BIT A D CONVERTER WITH TRACK HOLD MONOLITHIC SILICON《硅单片A D转换跑道 搁置8位互补型金属氧化物半导体线性微电路》.pdf（14页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Drawing updated to reflect current requirements. -rrp 02-07-18 R. MONNIN THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHET REV SHET REV STATUS REV A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A

2、 PREPARED BY RICK C. OFFICER DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY CHARLES E. BESORE COLUMBUS, OHIO 43216 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY MICHAEL A. FRYE MICROCIRCUIT, LINEAR, CMOS, 8-BIT, A/D CONVERTER WITH TR

3、ACK/HOLD, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 91-10-02 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-89518 SHEET 1 OF 13 DSCC FORM 2233 APR 97 5962-E507-02 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.Provided

4、 by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89518 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirem

5、ents for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89518 01 R X Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish

6、 (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Total Device type Generic number Circuit function unadjusted error 01 AD7821 CMOS 8-bit ADC with track/hold 1.0 LSB 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as foll

7、ows: Outline letter Descriptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20 Dual-in-line 2 CQCC1-N20 20 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ Supply voltage to ground (VSS) . 0

8、 V dc to 7.0 V dc Supply voltage to ground (VDD) 0 V dc to +7.0 V dc Digital input voltage -0.3 V dc to VDDDigital output voltage -0.3 V dc to VDDPositive reference voltage (VREF+) VSS 0.3 V dc, VDD+ 0.3 V dc Negative reference voltage (VREF-) . VSS 0.3 V dc, VDD+ 0.3 V dc Input voltage (VIN) . VSS

9、0.3 V dc, VDD+ 0.3 V dc Storage temperature range . -65C to +150C Lead temperature (soldering, 10 seconds) . +300C Power dissipation (PD) 450 mW 2/ Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Junction temperature (TJ) . +150C 1.4 Recommended operating conditions. Supply voltage to gro

10、und (VSS) . -4.75 V dc to 5.25 V dc Supply voltage to ground (VDD) . +4.75 V dc to +5.25 V dc Ambient operating temperature range (TA) . -55C to +125C Positive reference voltage (VREF+) VREF-to VDDNegative reference voltage (VREF-) . VSSto VREF+1/ All voltages are with respect to ground. 2/ Derate a

11、bove TA= +75C at 6.0 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89518 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS

12、 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Spe

13、cifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - In

14、terface Standard Electronic Component Case Outlines. HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standar

15、dization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes

16、applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that i

17、s produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in

18、accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML

19、“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline(s). T

20、he case outline(s) shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I a

21、nd shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF

22、-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked as listed in MIL-HDBK-103 (see 6.6 herein). For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the

23、 option of not marking the “5962-“ on the device. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89518 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97

24、TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ 2/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Resolution Res This is the minimum resolution for which no missing codes are guaranteed. 1,2,3 01 8.0 Bits Total unadjusted error T

25、UE 3/ 1,2,3 01 1.0 LSB Analog input leakage current IIN1,2,3 01 3.0 A Reference input resistance RIN1,2,3 01 1.0 4.0 k CS and RD inputs, VIH= 5.25 V, VIL= 0 V 1.0 WR input, VIH= 5.25 V, VIL= 0 V 3.0 Digital input high current IIHMode input, VIH= 5.25 V, VIL= 0 V 1,2,3 01 200 A Digital input low curr

26、ent IILCS , WR , RD and mode inputs 1,2,3 01 -1.0 A Digital output high level voltage VOHDB0-DB7, OFL , and INT outputs, ISOURCE= -360 A 1,2,3 01 4.0 V Digital output low level voltage VOLDB0-DB7, OFL , and INT outputs, ISINK= 1.6 mA 1,2,3 01 0.4 V Floating state leakage current IOUTDB0-DB7, VOUT= 5

27、.25 V, then VOUT= 0 V 1,2,3 01 3.0 A Supply current from VDDIDDCS = RD = 0 V 1,2,3 01 20.0 mA CS , WR and RD inputs 0.8 Digital input low level voltage VILMode input 1,2,3 01 1.5 V CS , WR and RD inputs 2.4 Digital input high level voltage VIHMode input 1,2,3 01 3.5 V Power supply sensitivity PSS VD

28、D= 5.0 V 5%, VREF= 4.75 V maximum 1,2,3 01 0.25 LSB Signal to noise ratio SNR 4/ 5/ 1,2,3 01 45 dB Total harmonic distortion THD 4/ 5/ 1,2,3 -50 Peak harmonic or spurious noise 4/ 5/ 1,2,3 01 -50 dB Second order terms 5/ 6/ -50 Intermodulation distortion IMD Third order terms 5/ 6/ 1,2,3 01 -50 dB S

29、upply current from VSSISSCS = RD = 0 V 1,2,3 01 100 A See footnotes at end of table.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89518 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVE

30、L A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 1/ 2/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Digital input capacitance CIDCS , WR , RD and mode inputs, See 4.3.1c, TA= +25C 4 01 8.

31、0 pF Analog input capacitance CIASee 4.3.1c 4 01 55 pF Digital output capacitance COUTSee 4.3.1c, TA= +25C 4 01 8.0 pF Slew rate, tracking SR 4/ 5/ 7,8 01 1.6 V/s 9 160 RD pulse width tREAD1Determined by tACC17/ 8/ 10,11 01 240 ns 9 65 RD pulse width tREAD2Determined by tACC27/ 8/ 10,11 01 85 ns CS

32、to RD / WR setup time tCSS7/ 8/ 9,10,11 01 0 ns CS to RD / WR hold time tCSH7/ 8/ 9,10,11 01 ns 9 70 CS to RDY delay tRDYCL= 50 pF, 8/ pull-up resistor = 4.7 k 10,11 01 100 ns 9 700 Conversion time ( RD mode) tCRD8/ 10,11 01 975 ns 9 750 Data access time ( RD mode) tACCO8/ 9/ 10,11 01 1050 ns 9 80 R

33、D to INT delay ( RD mode) tINTHCL= 50 pF 8/ 10,11 01 90 ns 9 60 Data hold time tDH8/ 10/ 10,11 01 80 ns 9 350 Delay time between conversion tP7/ 8/ 10,11 01 500 ns 9 0.25 10 Write pulse width tWR7/ 8/ 10,11 01 0.4 10 s 9 250 Delay time between WR and RD pulses tRD7/ 8/ 10,11 01 450 ns 9 185 Data acc

34、ess time ( WR / RD mode) tACC18/ 9/ 10,11 01 275 ns 9 150 RD to INT delay tR18/ 10,11 01 220 ns 9 500 WR to INT delay tINTLCL= 50 pF, see figure 3 11/ 10,11 01 700 ns 9 90 Data access time ( WR / RD mode) tACC28/ 9/ 10,11 01 130 ns 9 80 WR to INT delay (stand alone operation) tIHWRCL= 50 pF 8/ 10,11

35、 01 120 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89518 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I.

36、 Electrical performance characteristics Continued. Test Symbol Conditions 1/ 2/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max 9 45 Data access time after INT (stand alone operation) tID8/ 9/ 10,11 01 70 ns 1/ Unless otherwise specified, VDD= +5.0 V; VREF+

37、= +5.0 V; VREF-= GND = 0 V and VSS= 0 V. 2/ All input control signals are specified with tR= tF= 20 ns (10% to 90% of +5.0 V) and timed from a voltage level of 1.6 V. 3/ Includes gain error, offset error and linearity error. 4/ VIN= 99.85 kHz full scale sine wave at 5.0 V peak to peak with f samplin

38、g = 500 kHz. 5/ VSS= -5.0 V; VDD= +5.0 V; VREF+= +2.5 V; VREF-= -2.5 V. 6/ fa (84.72 kHz) and fb (94.97 kHz) combine to produce a full scale sine wave at the analog input with f sampling = 500 kHz. 7/ Pass/fail tested only with tested parameter used as a test condition. 8/ Refer to timing diagram of

39、 figure 3. These parameters are tested to subgroup 9 under group A test requirements. 9/ Measured with load circuits of figure 2 and defined as the time required for an output to cross 0.8 V to 2.4 V. 10/ Defined as the time required for the data lines to change 0.5 V when loaded with the circuits o

40、f figure 2 and is measured only for initial test and after process or design changes which may affect tDH. 11/ If not tested, shall be guaranteed to the limits specified in table I herein. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in

41、 compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufactu

42、rer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requ

43、irements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required in accordance with MIL-PR

44、F-38535, appendix A. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for R

45、esaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89518 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 Device type 01 Case outlines R and 2 Terminal number Terminal symbol 1 VIN

46、2 DB0(LSB) 3 DB14 DB25 DB36 WR /RDY 7 Mode 8 RD 9 INT 10 GND11 VREF-12 VREF+13 CS 14 DB415 DB516 DB617 DB7(MSB) 18 OFL 19 VSS20 VDDFIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 59

47、62-89518 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 8 DSCC FORM 2234 APR 97 Pin Function Description Pin Symbol Description 1 VINAnalog input. Range: VREF- VIN VREF+2 DB0Three-State Data Output (LSB) 3-5 DB1- DB3Three-State Data Outputs. 6 WR /RDY WRITE control i

48、nput/READY status output. 7 MODE Mode Selection Input. It determines whether the device operates in the WR-RD or RD mode. This input is internally pulled low through a 50 A current source. 8 RD READ input. RD must be low to access data from the part. 9 INT INTERRUPT Output. INT going low indicates that the conversion is complete. INT returns high on the rising edge of CS or RD . 10 GND Ground 11 VREF-Lower limit of reference span. Range: VSS VREF-tINTL) FIGURE 3. Mod