DLA SMD-5962-89516-1989 MICROCIRCUITS DIGITAL CMOS DUAL SERIAL I O CONTROLLER MONOLITHIC SILICON《硅单片双串行输入 输出控制器互补型金属氧化物半导体数字微电路》.pdf

《DLA SMD-5962-89516-1989 MICROCIRCUITS DIGITAL CMOS DUAL SERIAL I O CONTROLLER MONOLITHIC SILICON《硅单片双串行输入 输出控制器互补型金属氧化物半导体数字微电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-89516-1989 MICROCIRCUITS DIGITAL CMOS DUAL SERIAL I O CONTROLLER MONOLITHIC SILICON《硅单片双串行输入 输出控制器互补型金属氧化物半导体数字微电路》.pdf（23页珍藏版）》请在麦多课文档分享上搜索。

1、DESC-DWG-87516 57 m 7777775 0035233 4 v a II 7-52-35 PMIC MA STANDARDIZED MILITARY DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMEKT OF DEFENSE AMSC NIA I PREPAREDBY Ai. I - DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 25 JANUARY 1989 67268 15962-895

2、16 23 REVISION LEVEL SHEEt 1 OF DSC FORM 193 t US. GOVERHMfNl PRINTING OiFKf: 1987 - 748-11916091 1 SEP 87 5962-Ell46 DISTRIBUTION STATEMENT A. Approved for publlc release; dislribullon Is unlimited. f -. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,

3、-,-I I SIZE A 5962-89516 STANDARDIZED MILITARY DRAWING DEFENSE UECTRONICC SUPPLY CEHTER RMSM LEVEL SHEET DAYTON, OHIO 45444 2 b DESC-DWG-89516 57 9799775 OL523C6 1. SCOPE 1.1 Scope. This drawing describes device requirements for class 6 microcircuits in accordance with 1.mf MIL-STD-883, “Provisions

4、for the use of MIL-STD-883 in conjunction with compliant non-JAN devices“, 1.2 Part number. The complete part number shall be as shown in the following example: X T 7- 5962-89516 I I i Lead finish per i Case outline i Device type i Drawing number (1.21) (1.2.2) MIL-M-38510 1.2.1 Device type, The dev

5、ice type shall identify the circuit function as follows: Device type Generic number Clock frequency Circuit function o1 Z84C4206 6.17 MH2 Dual serial input/ output control ler 1.2.2 Case outline, The case outline shall be as designated in appendix C of MIL-M-38510, and as follows: I Outline letter Q

6、 Case outline 0-5 (40-lead, 2.096“ x ,620 x .225“) dual-in-line package 1.3 Absolute maximum ratings. V supply volta e range (VCC - GND)- - - - - - - - - #tage on any p!n (referenced to ground) - - - - - - -0.3 V dC to +7 V dc -0.3 V dc to *7 V dc -65C to +15OoC 1.0 +270 C +17OoC See MIL-M-38510, ap

7、pendix C Storage temperature range - - - - - - - - - - - - - - Lead temperature (soldering, 5 seconds) - - - - - - - Maximum junction tem erature (TJ) - - - - - - - - - - Thermal resistance, Junction to case (0JC)- - - - - - blaximum power disslpation (PD) - - - - - - - - - - 1.4 Recommended operati

8、ng conditions. 4.5 V dc minimm to 5.5 V dc maximum 2.2 V dc 0.8 V dc 0.45 V dc DC to 6.17 MHz -55C to +125C 20 ns maximum 20 ns maximum VCC -0.6 V dc Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DESC-DWG-8753b 57 m 7777775 0035235 B = SIZE A STAND

9、ARDIZED 2. APPLICABLE DOCUMENTS 5962-89516 2.1 Government specification and standard. Unless otherwise specified, the following pecification and standard, of the issue listed in that issue of the Department of Defense Index of aecifications and Standards specified in the solicitation. form a part of

10、 this drawing to the li tent specified herei n. SPEC IF I CATI ON MILITARY MI L-M-38510 - Microcircuits, General Specification for. STANDARD MILITARY MIL-STD-883 - Test Methods and Procedures for Microelectronics. (Copies of the specification and standard required by manufacturers in connection with

11、 specific icquisition functions should be obtained from the contracting activity or as directed by the ontracti ng activity.) ,eferences cited herein, the text of this drawing shall take precedence. 2.2 Order of precedence, 3. REQUIREMENTS 3.1 In the event of a conflict between the text of this draw

12、ing and the Item requirements. The individual item requirements shall be in accordance with 1.2.1 of IIL-STD-8 ind as sps:ified herein. “Provtsions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices“ 3.2 Design, construction, and physical dimensions. The design, construction, a

13、nd physical limensions Shall be as specitiea in MIL-M-JSlU and herein. 3.2.1 Terminal connections. 3.2.2 Case outline. The case outline shall be in accordance with 1.2.2 herein. The terminal connections shall be as specified on figure 1. 3.3 Electrical performance characteristics. Unless otherwise s

14、pecified, the electrical berformance characteristics are as specified in table I and apply over the full case operating :emperatwe range. be markGlTEL the part number listed in 1.2 herein. iay also be marked as listed in 6.5 herein. n order to be listed as an approved source of supply in 6.5. ubmitt

15、ed to DESC-ECS prior to listing as an approved source of supply shall state that the tanufacturers product meets the requirements of MIL-STD-883 (see 3.1 herein) and the requirements ierein. 3.4 Marking. Marking shall be in accordance with MIL-STD-883 (see 3.1 herein). The part shall In addition, th

16、e manufacturers part number 3.5 Certificate Of compliance. A certificate of compliance shall be required from a manufacturer The certificate of compliance 3.6 Certificate of conformance. A certificate of conformance as required in MIL-STD-883 (see 3.1 ierein) shall be provided with each lot of micro

17、circuits delivered to this drawing. 3.7 Notification of change. Notification of change iith MIL-STD-883 (see 3.1 herein). to DESC-ECS shall be required in accordance I Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DESC-DWG-8451b 54 4444475 O015236

18、T I . - TABLE I. Electrical performance characteristics. I I I I I Limits I -55OC TC +125OC I Group A IReference IRn I Max I I I I Vcc 5.07 *lo% Isubgroups I number f I I I I unless otherwise specified I I III I I I I III Conditions I I I I Unit Pa rame ter Clock input low !VIL1 I vol tage I I I vol

19、 tage I I I I Ii,2,3 I I t I I III I 1-0.3 gi 10.45 I V IV c rvc t I v LE Y io,$ VI Clock input high IVHI I I I, 2, 3 I I I I I III Input low voltage IVIL I I 1, 2, 3 I 1-0.3 0.8 I V I I I 1 t /i I I I I I III I 1, 2, 3 I I I I I I I I I fll Input high voltage 1V12 i III t 2.2 I vcc I v I I i I 10.4

20、1V I I I Output low voltage I 1, 2, 3 Out ut high vo! tage Output high voT tage Power supply current Power supply current Output 1 eakage current low, open drain outputs Output leakage current high, open drain outputs VOH 1 L vOH2 1 fCC1 I 1 Icc2 *LOL ILOH I I I 1 I I I 1 I I I I I I I I 1 I I I I 7

21、 I I I 1 1 I I IOH i: -1.6 IIA I 1, 2, 3 I I I I I I l, 2, I IOH = -250 NA I I I ee footnotes at end of table. I I I I I I I I I I I I I I VOUT = 0.4 V I 1, 2, 3 I VOUT = 2.4 v i 1, 2, 3 1 I I 2.4 I I IV II $!8 1 1 V II I I Il5 I InR i II I II loo I NA I1 -10 It10 I NA II I I i -10 It10 I NA II II I

22、I - SIZE A 5962-89516 STANDARDIZED MILITARY DRAWING REvIs1oN LEVEL SHEET EFENSE ELECTRONICS SUPPLY CENTER DAYIWN, OHIO 45444 4 ESC FORM 193A +U.8.6ovEwIpRIN7lHGoFFIcE1w f = 1 MHz I I I171 Output Capacitance; Co I I I directional 1 I I I I -10 I+10 I pA III I I I I III I I I IVIN = 2.4 V I 1, 2, 3 I

23、I I I IUnmeasured pins returned to I I I I I I151 I I III I m I I10 I I I I I I I I III I I I I I I I 7,8 I III I I I I I I I I ll I I I I I III Isee 4.3.1 I41 , I /PF I ground I“ 4*3*1d I I I II Input capacitance I CI Functional tests Maximum frequency IfMAx I CL = 100 pF *lo% 19, 10, 11 I I 6.171

24、3/ I I I I I MHz I I Ps I I ins I 330 I I ns - i/ I I I Clock cycle time ltcyci I - I 19, 10, 11 I 1 I 162 1 4/ y I I I I - I I - 19, 10, 11 I 24 I 330 I 19, 10, 11 I 30 TxC cycle time Itcyc I I Rx(: cycle time It.cyc3 I I Clock fall time Itfc I I I I i/ I I I I I I I III - i/ I I I I I I I III - 19

25、, 10, 11 I 3 I I ! 2o ! ns I III i/ I I I I - See footnotes at end of table. DESC-DWG-875Lb 57 W 7777775 O035237 L . I SIZE A 5962-89516 STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVU SHEET DAYTON, OHK) 45444 5 Provided by IHSNot for ResaleNo reproduction or networking

26、 permitted without license from IHS-,-,-TABLE I. Electrical performance characteristics - Continued. I I I I I Limits I I I Conditions I I I I Unit I I unless otherwise specified I I III I I III I I 19, 10, 11 I 4 I 20 I ns Clock rise time ItrC i/ I I I I III I I III Clock width hlgh Itp“1 I 19, 10,

27、 11 I 2 1 65 1 ns i/ y I I I I II I I III I I -1 19, 10, 11 5 1 65 I Clock width low ItpwL1 I I I I III I I v- II 19, 10, 11 I 22 1 200 I PulSe width hi h Itpw2 I I I I 1/ I I I I III I I I I III I Pulse width low ltpu2 I 19, 10, 11 I 23 200 ns I TX Width high Itp3 I II mwidth low Itpwj f -55C TC +1

28、25C I Group A IReference Imin I Max I I Vcc 5.0 V *lo% Isubgroups I number I I I fSymbo1 -I Parameter I CL = 100 pF *lo% 31 I - - I I nc I I ins - i/ I (rn, m, ?ubgroups I number I I I I I I I I iii ns 9, 10, 11 I 9 I 30 I I III I I II I III I I 9, 10, 11 I 33 I 0 I I ns III I I I III I III I I I I

29、I I I ns !-loo I I 9, 10, 11 ! 38 i iii 9, 10, 11 I 34 I 100 I I ns I I I I 150 I 9, 10, 11 I 8 I I I I I I I I I I 9, io, 11 I io I I 90 I ns I III I III I I III I III I III I I 120 I ns 9, 10, 11 I 11 9, 10, 11 I 27 I I 220 I ns I III ;ee footnotes at end of table. Provided by IHSNot for ResaleNo

30、reproduction or networking permitted without license from IHS-,-,-* TABLE I, Electrical performance characteristics - Continued. I I I I I Limits I I I Conditions I I I I Unit Parameter ISpbol 1 -55*C 5 TC +125C I Group A IReference IMTITKl I VCC = 5.0 V *lo% Isubgroups I number I I I I i unless oth

31、erwise saecified i I I II I I I I III 7- RT +to IEOc delay tpHL4 CL = 100 pF *lo% A/ 10, 11 I 14 I I 160 I ns I -1 19, I I III I I I I -I- l I I III I i Interrupt I before MI) L/ I (After ED decade)l 19, 10, 11 I 15 I I 70 I ns IEI* to IEO* ItPLH4 I I I I I III II IEIc to IEO+ -1 Clock+ tom* ltpHL6

32、I 19, 10, 11 I 17 I I 200 I ns il W“f delay I il Clock+ tom* I I mode) L/ I II Clock+ to ?47Rl5Y ItpLZ2 -1 I 19, 10, 11 I 16 del ay ItPHL5 I I I I I I I III delay L/ I I 1 III I I I I Il! II I I I 175 i Ili I I l7O I (Wait mode) L/ I I I I I I I I I m* tOE+ to tPHL7 III I I I delay (Ready I I I 19,

33、io, 11 i 20 I 1 110 I ns 19, 10, 11 I 28 (Wait mode) L/ I I I I III I float delay I 5 I 9 I !/ I I I I III I I I I II I m* to INT+ ItpHL10 I 19, 10, 11 I 29 I 5 I 9 I ?/ I 10 I 13 I 8/ -II I I I I m* to m+- (tpHL9 I delay (Ready mode) L/ delay L/ l I I I III 19, 10, 11 I 35 I m* to m+ ItpHL11 I dela

34、y (Ready I I l I I I- I I I I mode) L/ See footnotes at end of table. SIZE A 5962-89516 STANDARDIZED MILITARY DRAWING WEET DEFENCE ELECTRONICS SUPPLY CE“ RAYION, OHIO 45444 8 )ESC FORM 193A *u s. OWERNMENT PIOMIM OFFICE 1ws0-w SEP 87 Provided by IHSNot for ResaleNo reproduction or networking permitt

35、ed without license from IHS-,-,-DESC-DWG-87516 57 7777775 00152Yl 3 W SIZE A STANDARDIZED TABLE I a Electrical performance characteristics - Continued. 5962-89516 - I I I I I Limits I -55C TC +125C I Group A IReference ihin I Max I I I Vcc Y 5.0 V *lo% Isubgroups I number I I I I I unless otherwise

36、specified I I I II I I I I III Conditions I I I I Unit Parameter 13 I 8/ Il0 I I - to m+ ItpHL12 I CL = 100 pF *lo% - 3/ de ay L/ I I I I I III m+ torn+ ItpHL13 I I I III del ay (output I 19, 10, 11 I 37 I 4 I 7 I y mode) L/ I I I I III I I I I I II - i/ If not tested, shall be guaranteed to the spe

37、cified limits. 21 The reference number refers to the position where the parameters being tested appears on - figure 2. 31 Figure 2 represents the electrical performance characteristics associated with the ac 1 hits - shown in tab1 e I. - 4/ In all modes, the system clock rate must be at least five t

38、imes the maximum data rate. - 5/ RESET must be active a minimum of one complete clock cycle. 0 tPWH1 = tCYC - tPWL1 - tri: - tfC L/ tPWL1 = tCYC - tPWH1 - t, - tfC - 8/ Clock periods (system clock). 3.8 Verification and review. iview the manufacturers facility and applicable required documentation.

39、Offshore documentation hall be made available onshore at the option of the reviewer. DESC, DESCs agent, and the acquiring activity retain the option to 4. QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection. xtion 4 of MIL - M 58510 t o the extent specified in MIL-STD-883 (see 3.1 herein). Samp

40、ling and inspection procedures shall be in accordance with 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be mducted on al 1 devices prior to quality conformance inspection. The following additional criteria hall apply: a. Burn-in test, method 1015 of MIL-

41、STD-883. (1) Test condition D using the circuit submitted with the certificate of compliance (see 3.5 herein). (2) TA = +125.“C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional

42、at the discretion of the manufacturer. ii U. 8. QOVERHMENT PRINTING OFFCE 1888-593447 ESC FORM 193A SEP 87 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-. 03 4-+ DS u DI Im - IEI 4 IEO + m- vcc - W/RouA t SYNCA c-, RXDA -e RxCA - TCA -.+ TXDA + DTA

43、 t mA + CiSA -L DCOA _c CLOCK - I 2 3 4 5 6 7 8 9 IO II 12 13 14 15 16 17 18 19 20 Device type O1 39 30 37. 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 DI DO - D2 - 04 - O6 .*- m + CE t- B/n: c- C/O m W/RDYB - RxCB + m - GND RxDB TXDB + DTRB -b RXB - Cise t bcoe 7 *- RESET CASE O FIGURE 1. Termi

44、nal connections (top view). I 8128 A 5962-89516 STANDARDIZED MILITARY DRAWING DEFENCE UECIRONICS SUPPLY CENTER SHEET DAYTON. OHK) 4!j444 10 I DESC FORM 193A SEP a7 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-Switching test circuits Standard test

45、load Open drain test load cnnu I nwv OUTPUT UNDER TEST 250 pA 100 fl pF - - - t5 v T 2.2 k n $ 2.2 k 42 FROM OUTPUT UNDER TEST - Switching test input output waveform 2.4 2.k TEST d2.0 POINTS-. .45 AC testing: Timing nieasureinents ate made at 2.0 V for a logic “1“ and 0.8 V for logic “O“. Inputs are

46、 driven at 2.4 V for a logic “1“ and 0.45 Y for a logic “O“. FIGURE 2. Switching test circuits and waveforms. STANDARDIZED SIZE MILITARY DRAWING A 5962-89516 DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVU SHEET DAYTON, OHIO 45444 11 fi U. S GOVERNMFNTPRINIING OFFICE iQM-S590-Ml 3SC FORM 193A SEP 87

47、 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-Read cycle SIZE A STANDARDIZED CLK 5962-89516 IORO I DATA NOTE: Optional condition occurs only when any combination of these inputs must change state to reprogram during read/write operation. FIGURE 2.

48、 Switching test circuits and waveforms - Continued, Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-Write cycle kl-4 -121c+lL4 344-5 k-64 I CE ,C/O, B / I I I / 1m I/ I I - MI HIGH I DATA IN FIGURE 2. Switching test circuits and waveforms - Continued. STANDARDIZED MILITARY DRAWING lYI 8951 6 I SHEET REVISION LEVEL DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHK) 45444 13 DESC FORM 193A *U. S.QOVERNMOVTPRIMING OFFiCE: 1W-5M-547 SEP 87 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-I