DLA SMD-5962-89514 REV B-2013 MICROCIRCUIT DIGITAL CMOS PARALLEL I O CONTROLLER MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update boilerplate to current MIL-PRF-38535 requirements. - CFS 06-02-27 Thomas M. Hess B Update boilerplate to current MIL-PRF-38535 requirements. - PHN 13-06-06 Thomas M. Hess THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHEE

2、T REV B B B B B B B B SHEET 15 16 17 18 19 20 21 22 REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Greg A. Pitz DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY

3、 Ray Monnin THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, DIGITAL, CMOS PARALLEL I/O AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 89-01-05 CONTROLLER, MONOLITHIC SILICON AMSC N/A REVISION LEVEL SIZE A CAGE CODE 67268 5962-89514 B SH

4、EET 1 OF 22 DSCC FORM 2233 APR 97 5962-E444-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89514 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1

5、 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89514 01 Q X Drawing number Device type (s

6、ee 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Frequency Circuit function 01 Z84C2006 6.17 MHz Parallel input/output controller 1.2.2 Case outline(s). The case outline(s) are as

7、designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style Q GDIP1-T40 or CDIP2-T40 40 Dual-in-line 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. VCCsupply voltage range (referenced to grou

8、nd) -0.3 V dc to +7.0 V dc Voltage on any pin (referenced to ground) -0.3 V dc to +7.0 V dc Storage temperature range . -65C to +150C Maximum power dissipation 1.0 W 1/ Lead temperature (soldering, 10 seconds) +270C Maximum junction temperature (TJ): At TC= +125C +180C Thermal resistance, junction-t

9、o-case (JC) See MIL-STD-1835 1.4 Recommended operating conditions. Supply voltage range 4.5 V dc to 5.5 V dc Minimum high level input voltage (VIH): Logic inputs 2.2 V dc Clock input . VCC 0.6 V dc Maximum low level input voltage (VIL): Logic inputs 0.8 V dc Clock input . 0.45 V dc Frequency of oper

10、ation . DC to 6.17 MHz Case operating temperature range (TC) -55C to +125C Clock rise and fall times 20 ns maximum _ 1/ Must withstand the added PDdue to short circuit test; e.g., IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIR

11、CUIT DRAWING SIZE A 5962-89514 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the exten

12、t specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method

13、Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla

14、.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094). 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawin

15、g takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B dev

16、ices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufa

17、cturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modific

18、ations shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified

19、 in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Block diagram. The block diagram shall be as specified on figure 2. 3.2.4 Timing wave

20、forms and test circuits. The timing waveforms and test circuits shall be as specified on figure 3. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temper

21、ature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the

22、 PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. Provided by IHSNot for ResaleNo reproduction o

23、r networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89514 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices bu

24、ilt in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a man

25、ufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535,

26、appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime-VA sha

27、ll be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritime s agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made av

28、ailable onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89514 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Ele

29、ctrical performance characteristics. Test Symbol Conditions -55C TC +125C 4.5 V dc VCC 5.5 V dc unless otherwise specified Group A subgroups Device type Limits Unit Min Max Clock high input voltage VIH11, 2, 3 All VCC 0.6 VCC+ 0.3 1/ V Clock low input voltage VIL1-0.3 1/ 0.45 V Logic input high volt

30、age VIH22.2 VCC1/ V Logic input low voltage VIL2-0.3 1/ 0.8 V Logic low output voltage VOLIOL= 2.0 mA 0.4 V Logic high output voltage VOH1IOH= 1.6 mA 2.4 V Logic high output voltage VOH2IOH= -250 A VCC 0.8 V Power supply current ICC1VCC= 5.0 V, CLK = 6 MHz, VIH= VCC 0.2 V, VIL= 0.2 V, CL= 100 pF 7 m

31、A Power supply current ICC2VCC= 5.0 V, CLK = 0 MHz 100 A Output leakage current low, open drain outputs ILOLVOUT= 0.4 V -10 +10 A Output leakage current high, open drain outputs ILOHVOUT= VCC-10 +10 A Input low current (input and bidirectional) IILVIN= 0.4 V -10 +10 A Input high current (input and b

32、idirectional) IIHVIN= VCC-10 +10 A Darlington drive current port B only 1/ IOH2VCC= 4.5 V, VOH= 1.5 V, RL= 1.1 k -1.5 -5.0 mA Clock input capacitance CI1See 4.3.1c 4 10 pF Logic input capacitance CI24 5 pF Output and bidirectional capacitance CO4 15 pF Functional test See 4.3.1d 7, 8 See footnotes a

33、t end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89514 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteris

34、tics - Continued. Test Symbol Conditions -55C TC +125C 4.5 V dc VCC 5.5 V dc unless otherwise specified Group A subgroups Refer-ence number Device type Limits Unit Min Max Maximum frequency 1/ fMAXSee figure 3. CL= 100 pF 10% 9, 10, 11 All 6.17 MHz Clock cycle time tcyc2/ 1 162 ns Clock pulse width

35、high tPWH12 65 ns Clock pulse width low tPWL13 65 ns Clock time, fall 1 tfc4 20 ns Clock time, rise 1/ trc5 20 ns CE, B/A, C/D to RD, IORQ setup time tSHL16 50 3/ ns Any hold times for specified setup time 1/ tHLH1, tHHL17 35 ns RD, IORQ to clock setup time tSLH2, tSHL28 70 ns RD, IORQ to data out d

36、elay tPZL1, tPZH19 300 4/ ns RD, IORQ to data out float delay 1/ tPLZ1, tPHZ110 70 ns Data in to clock setup time tSZH1, tSZL1See figure 3. CL= 50 pF 10% 11 40 ns IORQ to data out delay (INTACK cycle) tPZL2, tPZH2See figure 3. CL= 100 pF 10% 12 120 4/ ns M1 to clock setup time 5/ tSHL313 70 ns M1 to

37、 clock setup time 5/ (M1 cycle) tSLH414 0 ns M1 to IEO delay (interrupt immediately proceeding M1) 1/ tPHL115 100 6/ 7/ ns IEI to IORQ setup time (INTACK cycle) 1/ tSHL516 100 ns IEI to IEO delay tPHL2See figure 3. CL= 50 pF 10% 17 120 6/ ns See footnotes at end of table. Provided by IHSNot for Resa

38、leNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89514 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -5

39、5C TC +125C 4.5 V dc VCC 5.5 V dc unless otherwise specified Group A subgroups Refer-ence number Device type Limits Unit Min Max IEI to IEO delay (after ED decode) tPLH3See figure 3. CL= 100 pF 10% 9, 10, 11 18 All 150 6/ ns IORQ to clock setup time (to activate READY on next clock cycle) 1/ tSLH619

40、 170 ns Clock to READY delay 1/ tPHL4See figure 3. CL= 50 pF 10% 20 170 6/ ns Clock to READY delay 1/ tPHL5See figure 3. CL= 100 pF 10% 21 120 6/ ns STROBE pulse width 1/ tPWL222 120 8/ ns STROBE to clock setup time (to activate READY on next clock cycle) 1/ tSHL723 150 6/ ns IORQ to PORT DATA stabl

41、e delay (mode 0) tPZL3, tPZH324 160 6/ ns PORT DATA to STROBE setup time (mode 1) tSLH8, tSHL825 190 ns STROBE to PORT DATA stable (mode 2) tPZL4, tPZH426 180 6/ ns STROBE to PORT DATA delay (mode 2) 1/ tPLZ2, tPHZ2See figure 3. CL= 50 pF 10% 27 160 ns PORT DATA match to INT delay (mode 3) tPHL6See

42、figure 3. CL= 100 pF 10% 28 430 ns STROBE to INT delay tPHL729 350 ns 1/ Guaranteed, if not tested, to the limits specified herein. 2/ tcyc= tPWH1+ trc+tPWL1+ tfc. 3/ tSHL1may be reduced, however, the time subtracted must be added to tPZL1or tPZH1. 4/ Increase by 10 ns for each 50 pF increase in loa

43、d up to 200 pF maximum. 5/ To reset the PIO, M1 must be active for a minimum of 2 clock cycles without an active RD or IORQ signal. 6/ Increase by 2 ns for each 10 pF increase in load up to 100 pF maximum. 7/ 2.5 tcyc (N-2) tPHL2+ tPHL1+ tSHL5. 8/ For mode 2: tPWL2 tSLH8. Provided by IHSNot for Resa

44、leNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89514 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 Device type: 01 Case outline: Q Terminal number Terminal symbol Terminal number Termin

45、al symbol 1 D2 21 BRDY 2 D7 22 IEO 3 D6 23 INT 4 CE 24 IEI 5 C/D 25 CLK 6 B/A 26 VCC7 PA7 27 PB0 8 PA6 28 PB1 9 PA5 29 PB2 10 PA4 30 PB3 11 GND 31 PB4 12 PA3 32 PB5 13 PA2 33 PB6 14 PA1 34 PB7 15 PA0 35 RD 16 ASTB 36 IORQ 17 BSTB 37 M1 18 ARDY 38 D5 19 D0 39 D4 20 D1 40 D3 FIGURE 1. Terminal connect

46、ions. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89514 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 9 DSCC FORM 2234 APR 97 FIGURE 2. Block diagram. Provided by IHSNot for Resal

47、eNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89514 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 10 DSCC FORM 2234 APR 97 AC testing: Inputs are driven at 2.4 V for logic “1” and 0.45 V for logic “0”. Timing

48、measurements are made at 2.0 V for logic “1” and 0.8 V for logic “0”. FIGURE 3. Switching waveforms and test circuits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89514 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 11 DSCC FORM 2234 APR 97 FIGURE 3. Switching waveforms and test circuits - Continued. Prov