DLA SMD-5962-10208 REV A-2010 MICROCIRCUIT DIGITAL ASIC RADIATION HARDENED SOI CMOS SERIALIZER DESERIALIZER (SERDES) MONOLITHIC SILICON.pdf

《DLA SMD-5962-10208 REV A-2010 MICROCIRCUIT DIGITAL ASIC RADIATION HARDENED SOI CMOS SERIALIZER DESERIALIZER (SERDES) MONOLITHIC SILICON.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-10208 REV A-2010 MICROCIRCUIT DIGITAL ASIC RADIATION HARDENED SOI CMOS SERIALIZER DESERIALIZER (SERDES) MONOLITHIC SILICON.pdf（48页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED REV SHEET 35 36 37 38 39 40 41 42 43 44 45 46 47 REV SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 REV STATUS REV OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS

2、, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Phu H. Nguyen APPROVED BY Thomas M. Hess MICROCIRCUIT, DIGITAL, ASIC, RADIATION HARDENED, SOI CMOS, SERIALIZER/DESERIALIZER

3、 (SERDES), MONOLITHIC SILICON DRAWING APPROVAL DATE 10-09-01 AMSC N/A REVISION LEVEL SIZE A CAGE CODE 67268 5962-10208 SHEET 1 OF 47 DSCC FORM 2233 APR 97 5962-E472-10 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE

4、 A 5962-10208 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case ou

5、tlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 H 10208 01 V X C Federal stock class designator

6、 RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Leadfinish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA

7、 designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic num

8、ber Circuit function 01 HXSRD01T(Q or V)H Quad Redundant SERDES 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD

9、-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Packag

10、e style X See figure 1 468 Land Grid Array 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROC

11、IRCUIT DRAWING SIZE A 5962-10208 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Core supply voltage range. (VDD) . -0.5V to +2.5 V SSTL-2 Supply voltage, (VDD2) -0.5 V to +4.6 V Input voltage . -0.5 V to VDDx+ 0.5 V 2/ 3/

12、 Output voltage . -0.5 V to VDDX+ 0.5 V 2/ 3/ Maximum junction temperature . +175oC Thermal resistance, junction to case, (JC) . 1.36oC/W Storage temperature range. (TSTG) -65oC to +150oC ESD HBM . Class 1C Typical power dissipation 4/ Trivor Configuration 5/ 6/ 7/ 8/ 9/ 1.0625 Gbps (mW) 2.125 Gbps

13、(mW) 3.125 Gbps (mW) 3.1875 Gbps (mW) CMU only 10/ 221 306 410 425Single port 11/ 1087 1363 1766 1786 Single Lane 12/ 17/ 535 675 902 907 Single Transmit Port 13/ 484 612 806 810Single Transmit Lane 14/ 17/ 383 488 662 664 Single Receive Port 15/ 826 1057 1370 1400Single Receive Lane 16/ 373 493 650

14、 668 _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability 2/ VDDx(relevant supply) must be at recommended DC level. When VDDxis above recommended levels then absolute limits f

15、or inputs and outputs are capped by the limit for VDDx. 3/ Absolute maximum levels for cold spare I/O when VDDxis 0V are the same as the limit for the relevant VDDx. 4/ The power varies depending on the device configuration. Values below include the following test configuration settings: - Serial tr

16、ansmitter output amplitude : 1600 mV - PLL Divider setting: Div 10 - Line rate setting: Set as necessary to achieve proper data rate - Nominal/Default settings for: VDD, VDDA, Pre-Emphasis and equalization. 5/ SSTL-2 power is not included because it consumes power from the 2.5 V supply. 6/ SSTL-2 po

17、wer estimate is 450 mW per port or 112.5 mW per lane. 7/ Power number are based on transmitting and receiving the CJTPAT. 8/ The 1.8 V power consumptions includes the VDD and VDDA supply power which provides power to the SERDES macro and Trivor logic that is external to the SERDES macro. All SERDES

18、and Trivor Logic is included in this estimate. 9/ These are typical values and are not tested on a part-by-part basis. 10/ CMU power includes the PLL and associated clock trees in Trivor and SERDES8_TOP. 11/ Full port power includes both transmit and receive channels for 4 lanes and the CMU power. 1

19、2/ Full lane power includes both transmit and receive channels for 1 lane and the CMU power. 13/ Transmit port power includes only the transmit channels for 4 lanes and the CMU power. 14/ Transmit lane power includes only the transmit channels for 1 lane and the CMU power. 15/ Receive port power inc

20、ludes only the receive channels for 4 lanes and the CMU power. 16/ Receive lane power includes only the receive channels for 1 lane and the CMU power. 17/ The average power per transmit lane decreases as additional lanes are utilized within a port due to port level clock distribution overhead. Provi

21、ded by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10208 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 4 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. DC supply voltage range. (VD

22、D) +1.71 V to +1.89 V DC supply voltage range. (VDD2) +2.3 V to +2.7 V CMOS input signal voltage -0.3 V to VDDx+ 0.3 V CMOS output signal voltage . -0.3 V to VDDx+ 0.3 V LVPECL DC input signal voltage -0.13 V to VDDx + 0.3 V 18/ LVPECL differential input voltage . + 100 mV to VDD 19/ LVPECL DC commo

23、n mode voltage . 20/ Case temperature . -55oC to +125oC 1.5 Digital logic testing for device classes Q and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) 95.49 percent 1.6 Radiation features. Maximum total dose available (dose rate = 50 300 rads(Si)/s) 1E6

24、 Rads(Si) Heavy Ion Single event upset rate (Adams 10% worst case environment) 1x10-12Data Bit Errors/Bits Sent 21/ Proton Single event upset rate (Adams 10% worst case environment) . 2x10-12Data Bit Errors/Bits Sent 21/ Neutron irradiation 1E14 neutrons/cm222/ Dose rate data upset 1E10 Rad(Si)/sec

25、for 50 nsec Dose rate survivability . 1E12 Rad(Si)/sec for 50 nsec Latchup . Immune by SOI technology. 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unl

26、ess otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits.

27、 MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or fr

28、om the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) _ 18/ This specifies the maximum allowable DC delta between the two inputs 19/ This specifies the minimum input differential voltage required for switching. This differential voltage is ABS(VIN

29、P-VINN). 20/ These signals require AC coupling, therefore the Common Mode Voltage requirement is not applicable. 21/ The Bit Error Ratio (BER) is defined as the number of bit errors per bits sent due to ion-induced single event upsets. 22/ Guaranteed but not tested for 1 MeV equivalent neutrons. Pro

30、vided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10208 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 5 DSCC FORM 2234 APR 97 2.2 Non-Government publications. The following document(s) form

31、a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation or contract. AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM F1192 - Standard Guide for the Measurement of Single Event Phe

32、nomena (SEP) Induced by Heavy Ion Irradiation of Semiconductor Devices. (Copies of this document is available online at http:/www.astm.org/ or from ASTM International, P. O. Box C700, 100 Barr Harbor Drive, West Conshohocken, PA 19428-2959). ELECTRONICS INDUSTRIES ASSOCIATION (EIA) JEDEC Standard EI

33、A/JESD78 - IC Latch-Up Test. (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references c

34、ited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordan

35、ce with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-

36、PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein f

37、or device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Pin group translation table. The pin group translation table shall be as specified on fig

38、ure 3. 3.2.4 Block or logic diagram(s). The block or logic diagram(s) shall be as specified on figure 4. 3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be as specified on figure 5. 3.2.6 Burn in circuit. The burn in circuit shall be as specified on figure 6. 3.2.7 SSTL-2 AC t

39、iming waveforms. The SSTL-2 AC timing waveforms shall be as specified on figure 7-12. 3.2.8 Functional tests. Various functional tests used to test this device are contained in the figure 7. If the test patterns cannot be implemented due to test equipment limitations, alternate test patterns to acco

40、mplish the same results shall be allowed. For device class M, alternate test patterns shall be maintained under document revision level control by the manufacturer and shall be made available to the preparing or acquiring activity upon request. For device classes Q and V, alternate test patterns sha

41、ll be under the control of the device manufacturers Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the preparing or acquiring activity upon request. The functional test vectors are listed in figure 7. Provided by IHSNot for ResaleNo reproduction or netw

42、orking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10208 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 6 DSCC FORM 2234 APR 97 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herei

43、n, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electric

44、al tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has th

45、e option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certif

46、ication/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of

47、 compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (s

48、ee 6.6.2 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this dr