DLA SMD-5962-08244 REV D-2013 MICROCIRCUIT DIGITAL RADIATION HARDENED 4-PORT SPACEWIRE ROUTER MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Change Differential output voltage, VOD, and Offset voltage, VOS, in Table I. - phn 11-05-18 David J. Corbett B Add case outline Y. Add minimum value for tTCVand maximum value for tRXH, in table IA. Update boilerplate to current MIL-PRF-38535 req

2、uirements. - PHN 13-05-14 Thomas M. Hess C Correct dimensions for A1 and b in case outline Y. - PHN 13-06-13 Thomas M. Hess D Correct pin name and add pin number for power and ground in terminal connection table, Figure 2. - PHN 13-08-13 Thomas M. Hess REV SHEET REV D D D D D D D D D D D D D D D SHE

3、ET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 REV STATUS REV D D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Ph

4、u H. Nguyen THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY David J. Corbett MICROCIRCUIT, DIGITAL, RADIATION HARDENED, 4-PORT SPACEWIRE ROUTER, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 11-04-06 AMSC N/A REVISION LEVEL SIZE A CAGE CODE 67268

5、 5962-08244 D SHEET 1 OF 29 DSCC FORM 2233 APR 97 5962-E540-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08244 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR

6、 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When

7、available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 R 08244 01 Q X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Le

8、ad finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identif

9、y the circuit function as follows: Device type Generic number Circuit function 01 1/ UT200SpW4RTR 4-Port SpaceWire router 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q

10、 or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1. 255 Ceramic Land Grid Array Y See figure 1. 255 Ceramic Column Grid Array

11、1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V. 1.3 Absolute maximum ratings. 2/ Core supply voltage range (VDDC) -0.3 V dc to 3.6 V dc I/O supply voltage range (VDD) -0.3 V dc to 4.5 V dc Voltage on any pin during operation (VI/O) . -0.3 V dc to (VDD+

12、 0.3 V dc) DC input current (II) . 10 mA Maximum power dissipation (PD) . 11 W Thermal resistance, junction-to-case (JC) . 4C/W Storage temperature range (TSTG) . -65C to +150C Maximum junction temperature (TJ) . 150C _ 1/ Device type 01 has restricted temperature range of -40C to +105C. 2/ Stresses

13、 above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A

14、 5962-08244 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. 3/ 4/ Core supply voltage range (VDDC) 2.30 V dc to 2.70 V dc I/O supply voltage range (VDD) 3.0 V dc to 3.6 V dc Input voltage range on any pin (VIN) . 0

15、V dc to VDDCase operating temperature range (TC) -40C to +105C Maximum rise or fall time: CMOS inputs: (VIL VIH) or (VIH VIL) . 20 ns LVDS inputs (VTH VTL) or (VTL-VTH) 20 ns 1.5 Radiation features. Maximum total dose available (dose rate = 50 300 rads(Si)/s) . 100 krads(Si) Single event latchup (SE

16、L) 100 MeV-cm2/mg Single event upset (SEU) saturated cross-section (sat) 1.1E-6 cm2/device Onset single event upset (SEU) linear energy threshold (LET), no upset . 28 MeV-cm2/mg Neutron fluence . 1E14 neutrons/cm25/ Dose rate upset . 6/ Dose rate survivability . 6/ 2. APPLICABLE DOCUMENTS 2.1 Govern

17、ment specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATI

18、ON MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Mi

19、crocircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/www.quicksearch.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) _ 3/ This device operates with a 2.5 V

20、core voltage supply and a 3.3 V I/O voltage supply. 4/ Power sequencing information: To avoid large surge currents, VDDshould be powered up either before VDDCor synchronously with VDDC(VDD VDDC). Do not power up the core voltage supply VDDC before the I/O supply VDD; doing so will cause a large in-r

21、ush current from VDDCto VDDthat will stress the power supplies and router components. For proper operation, connect all VDDpins to 3.3 V, VDDCpins to 2.5 V, and ground all VSSpins (i.e. no floating VDD, VDDC, or VSSinput power pins). It is also recommended that all inputs be driven, or biased, towar

22、d either VDDor VSS. If VDDand VDDCare being power up synchronously ensure that the voltage difference between VDDCand VDDdoes not exceed 0.4 V (VDDC VDD3.0 V; VDDC 2.25 V 9,10,11 0 ns Minimum number of full clock cycles (HOST_CLK) between rising edge of RSTand inputs valid 9/ tDRST3 Minimum number o

23、f full clock cycles (HOST_CLK) that RSTmust remain low before RSTcan transition high 9/ tCRST6 LVDS Driver 3/ 10/ 11/ Differential Skew (tPHLD tPLHD) tSKDDSee Figure 6 - 9 9,10,11 500 ps Rise time tRISED2.2 ns Fall time tFALLD2.2 LVDS data strobe output skew tCLKD tCLKS tDSSKEWLV1.0 ns LVDS Receiver

24、 3/ 10/ 11/ Data/Strobe separation tDSSEPSee Figure 10 - 12 9,10,11 3.5 ns LVCMOS SpW RECEIVE PORT (Figure 14) Data/Strobe separation tDSSEPCM9,10,11 3.5 ns LVCMOS SpW TRANSMIT PORT (Figure 13) Data strobe output skew tCLKD tCLKS tDSSKEWCM9,10,11 1.5 ns LVCMOS outputs rise time 9/ tTLHCM2.4 LVCMOS o

25、utputs fall time 9/ tTHLCM1.3 Host clock and SpW input clocks 12/ HOST_CLK frequency fHOSTSee Figure 10 9,10,11 2.5 50 MHz Space Wire ports input clock frequencies TXCLK_IN_1, TXCLK_IN_2, TXCLK_IN_3, and TXCLK_IN_4 fTXCLKIN10 200 MHz See footnotes at end of table. Provided by IHSNot for ResaleNo rep

26、roduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08244 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 9 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ 3.0 V

27、VDD 3.6 V 2.30 V VDDC 2.70 V -40C TC +105C unless otherwise specified Group A subgroups Limits Unit Min Max AC ELECTRICAL CHARACTERISTICS - CONTINUED Time code interface Time Code Data Setup time to HOST_CLK Rising Edge and TICK_IN High 13/ tTCDS See Figure 16 and 17 9,10,11 2 ns Time Code Data Hold

28、 time from HOST_CLK Rising Edge and TICK_IN High 13/ tTCDH0 TICK_IN Setup time to HOST_CLK Rising Edge and TIME_CODE Valid tTIS 2.5 TICK_IN Hold time from HOST_CLK Rising Edge and TIME_CODE Valid tTIH 0 Time from HOST_CLK Rising Edge to TIME_CODE valid 13/ 3/ tTCV5.75 15 Time from HOST_CLK Rising Ed

29、ge to TICK_OUT High tTHVH3 15 Time from HOST_CLK Rising Edge to TICK_OUT Low tTHVL3 15 TICK_OUT High to Low (HOST_CLK) 9/ 13/ tTOHL1.5 TICK_OUT High to Low (HOST_CLK) 9/ 13/ tTOLH1.5 Transmit FIFO Transmit Data Setup time to HOST_CLK Rising Edge (TX_PUSHand CSELValid Low) tTXSSee Figure 13 - 15 CL=

30、20 pF max 9,10,11 3 ns Transmit Data Hold time from HOST_CLK Rising Edge (TX_PUSHand CSELValid Low) tTXH0 Transmit PUSH Setup time to HOST_CLK Rising Edge and CSELLow tTXPUSHS6 Transmit PUSH Hold time from HOST_CLK Rising Edge and CSELLow tTXPUSHH0 Chip Select Setup time to HOST_CLK Rising Edge and

31、TX_PUSHLow tCSPUSHS12 Chip Select Hold time from HOST_CLK Rising Edge and TX_PUSHLow tCSPUSHH0 Almost Full to Full flag (TX_AFULL to TX_FULL) 9/ tALM2FULL8 #PUSHES Time from last transmit Push to TX_AFULL tXAF3 3/ 9.5 ns Time from last transmit Push to TX_FULL tTXF3 3/ 9.5 See footnotes at end of ta

32、ble. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08244 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 10 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics - Co

33、ntinued. Test Symbol Conditions 1/ 3.0 V VDD 3.6 V 2.30 V VDDC 2.70 V -40C TC +105C unless otherwise specified Group A subgroups Limits Unit Min Max AC ELECTRICAL CHARACTERISTICS - CONTINUED Receive FIFO Receive Data Hold time from HOST_CLK Rising Edge (RX_POPand CSELValid Low) 3/ tRXHSee Figure 21

34、and 22 CL= 20 pF max 9,10,11 3 12.25 ns Receive POP Setup time to HOST_CLK Rising Edge and CSELLow tRXPOPS3 Receive POP Hold time from HOST_CLK Rising Edge and CSELLow tRXPOPH0 Chip Select Setup time to HOST_CLK Rising Edge and RX_POPLow tCSPOPS13 Chip Select Hold time to HOST_CLK Rising Edge and RX

35、_POPLow tCSPOPH0 Almost Empty flag to Empty flag (RX_AEMPTY to RX_EMPTY) 9/ tALM2EMY8 # POPS Time from last Receive data POP to RX_AEMPTY tRXAE3 3/ 9.5 ns Time from last Receive data POP to RX_EMPTY tRXE3 3/ 9.5 Control inputs and reset Time from OElow to valid output data tRXOE See Figure 18 9,10,1

36、1 10 ns Time from CSELlow to valid output data tRXCS 10 Time from OEhigh to tri-state tRXOEZ 10 Time from CSELhigh to tri-state tRXCSZ 10 1/ RHA parts for device type 01 supplied to this drawing have been characterized through all levels M, D, P, L, and R of irradiation. However, this device is only

37、 tested at the R level. Pre and Post irradiation values are identical unless otherwise specified in Table IA. When performing post irradiation electrical measurements for any RHA level, TA= +25C. 2/ Current into device pins is defined as positive. Current out of device pins is defined as negative. A

38、ll voltages are referenced to ground except differential voltages. 3/ Guaranteed by characterization. 4/ Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. 5/ Capacitance is measured for initial qualification and when design changes may affect the

39、 input/output capacitance. Capacitance is measured between the designated terminal and VSSat a frequency of 1 MHz, and signal amplitude of 50 mV maximum. 6/ Functional tests conditions: VIH= VIH(min) +20%, - 0%; VIL= VIL(max) + 0%, -50%, as specified herein, for TTL, CMOS, or Schmitt compatible inpu

40、ts. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 7/ Supplied as a design limit but not guaranteed or tested. 8/ Not more than one output may be shorted at a time for maximum duration of one second. 9/ Guaranteed by desig

41、n. 10/ Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO= 50, tr 1 ns, and tf 1 ns. 11/ CLincludes probe and jig capacitance. 12/ HOST_CLK must run at 0.25X the fastest TXCLK_IN frequency. 13/ Time Code signals TIME_CODE7:6 are excluded Provided by IHSNot for ResaleNo reprod

42、uction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08244 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 11 DSCC FORM 2234 APR 97 TABLE IB. SEP test limits. 1/ 2/ Device type VDD= 3.0 V VDDC= 2.30 V 3/ Bias for latch-up test V

43、DD= 3.6 V VDDC= 2.70 V no latch-up LET = 4/ MeV/(mg/cm2) Effective LET no upsets MeV/(mg/cm2) Maximum bit cross section (cm2/device) All 28 1.1E-6 100 1/ For SEP test conditions, see 4.4.4.4 herein. 2/ Technology characterization and model verification supplemented by in-line data may be used in lie

44、u of end-of-line testing. Test plan must be approved by TRB and qualifying activity. 3/ Tested at worst case temperature, TA= +25C 10C. 4/ Tested at worst case temperature, TA= +105C 10C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICRO

45、CIRCUIT DRAWING SIZE A 5962-08244 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 12 DSCC FORM 2234 APR 97 Case outline X Dimensions Symbol Millimeters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min Max A 3.66 .144 D1/E1 19.05 TYP .750 TYP A1 2.57 3.12 .101 .123

46、e 1.27 BSC .050 BSC D/E 20.80 21.21 .819 .835 NOTES: 1. Lid is connected to VSS. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08244 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 R

47、EVISION LEVEL D SHEET 13 DSCC FORM 2234 APR 97 Case outline Y Dimensions Symbol Millimeters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min Max A 6.10 .240 D/E 20.80 21.21 .819 .835 A1 2.11 2.31 .083 .091 D1/E1 19.05 TYP .750 TYP A2 2.56 3.12 .101 .123 e 1.27 TYP .050 TYP b 0.46 0.66 .0

48、18 .026 NOTES: 1. Lid is connected to VSS. FIGURE 1. Case outline - Continued. 12345678910111213141516ABCDEFGHJKLMNPRTEb.010 SAeeDBA BTOP VIEWAC.008S S255 PLSA1A2AT CERAMIC.010 S CD1/E1Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUI