CEPT T CD 01-06 E-1985 Engineering Requirements for a 9600 Bit s Modem for Use on Leased Circuits《在租赁电路上使用的9600比特 秒调制解调器工程要求》.pdf

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1、CEPT T/CD*OL-Ob*E 77 m232bY1Y 0003104 Y W ci9 Page 1 E Recommendation T/CD 01-06 E (Ostende 1979, revised at Cannes 1983) concerning the engineering requirements for a 9,600 bit/s modem for use on leased circuits Recommendation proposed by Working Group T/WG 10 “Data Communications” (CD) Text of the

2、 revised Recommeiidation adopted by the “Telecommui-iications” Commission: “The Conference of European Post and Telecommunications Administrations, Considering - that Recommendation T/CD 01-01 contains the text of the Specifications of the general engineering requirements - that working group CD has

3、 studied under the auspices of Question CD 1 the harmonisation of data circuit for data circuit terminating equipment; terminating equipment. Recommends - that the attached Specification of engineering requirements for a 9,600 bit/s modem for use on leased lines as contained in Annex 1 to this Recom

4、mendation should be taken into account by all CEPT Administrations when implementation of such a piece of equipment is being planned by Administrations.” Administrations are free to stipulate additional requirements, and also which of the optional requirements, if any, are to be provided. The specif

5、ication is subject of continuing study and possible amendment. O Edition of November 30, 1985 CEPT T/CD*OL-Ob*E 79 W 2326434 0003105 b - T/CD 01-06 E Page 3 Annex 1. Contents Section A. Basic requirettients. 5 1. General . 5 2. Data signalling rates. . 5 3. Interfaces 5 4. Modulation and coding. 6 5

6、. Scrambling 9 6. Timing . 10 7. Backward channel. 10 8. Line signal levels . 10 9. Power consumption 11 10. Performance requirements . 11 Section B. National network dependant requirements O No special requirement. Section C. Optional requirements. . 12 1. Multiplexing . 12 Appendix I. Details of t

7、he pseudo-random sequence generator 15 Appendix II. Detailed scrambling and descrambliug process . 16 Edition of November 30. 1985 CEPT T/CD*OL-Ob*E 79 W 232643Ll 0003106 B W TfCD O1 -06 E Page 5 Section A. Basic reqriiretnetits 1. GENERAL The 9,600 bit/s modem is mainly intended for use on leased c

8、ircuits. Other applications need further study. The modem must meet the requirements given in the Specification of the general engineering requirements and in this specification. It must comply with CCITT Recommendations V.29 and V.24/V.28. This modem is intended to be used on special quality leased

9、 circuits, but this does not preclude the use of this modem on switched or leased circuits of lower quality, at the discretion of the concerned Administra- tion. The main characteristics of the recommended modem are as follows: - capability of operating in a duplex or half-duplex mode with continuou

10、s or controlled carrier; - combined amplitude and phase-modulation with synchronous mode of operation; - inclusion of an automatic adaptive equalizer; - optional inclusion of a multiplexer for combining data rates 7,200, 4,800 and 2,400 bits per second. 2. DATA SIGNALLING RATES The data signalling r

11、ates shall be 9,600, 7,200 and 4,800 bits per second +0.01%. The modulation rate is 2,400 bauds f0.01%. 3. INTERFACES 3.1. Interchange circuits The interchange circuits to be used are given in the list below. List of essential interchange circuits No. 1 Designation I 102 103 104 105 106 107 109 111

12、113 114 115 140 141 142 Signal ground or common return Transmitted data Received data Request to send Ready for sending Data set ready Data channel received line signal detector Data signalling rate selector (DTE source) Transmitter signal element timing (DTE source) Transmitter signal element timin

13、g (DCE source) Receiver signal element timing (DCE source) Loopback/Maintenance test Local loopback (Note 1) Test indicator (Note 2) The following notes apply only when the multiplixer option is installed. Note 1: Circuit 141 is present only on Port A. Looping occurs on all ports. Note 2: Circuit 14

14、2 is present on all ports of the multiplexer, but may be activated on an individual port -asis for individual port tests. All are activated simultaneously for entire DCE tests. The function of the above interchange circuits are defined in the Specification of the general -engineering requirements T/

15、CD 01-01 and comply with CCITT Recommendation V.24. 3.2. Electrical characteristics The electrical characteristics of the above interchange circuits are given in the Specification of the general engineering requirements T/CD 01-0 1 and comply with CCITT Recommendation V.28. Edition of November 30, 1

16、985 CEPT T/CD*OL-Ob*E 79 W 2326434 0003107 T T/CD O1 -06 E Page 6 4. MODULATION AND CODING 4.1. Line signais The carrier frequency is to be 1,700 + 1 Hz. 4.2. Signal space coding 4.2.1. At 9,600 bits per second, the scrambled data stream to be transmitted is divided into groups of four consecutive d

17、ata bits (quadbits). The first bit (Ql) in time of each quadbit is used to determine the signal element amplitude to be transmitted. The second (Q2), third (Q3) and fourth (Q4) bits are encoded as a phase change relative to the phase of the immediately preceding element (see Table 1/V.29.). 1 43 44

18、Phase change (see Note) O“ 45“ 90“ 135“ 180“ 225“ 270“ 315“ Table 1/V.29. Note: The phase change is the actual on-line phase shift in the transition region from the end of one signalling element to the beginning of the following signalling element. The relative amplitude of the transmitted signal el

19、ement is determined by the first bit (Ql) of the quadbit and the absolute phase of the signal element (see table 2/V.29). The absolute phase is initially established by the synchronizing signal as explained in 4.4.2. below. 4.2.2. At the fallback rate of 7,200 bits per second, the scrambled data str

20、eam to be transmitted is divided into groups of three consecutive data bits. The first data bit in time determines 42 of the modulator quadbit. The second and third data bits determine 43 and 44 respectively of the modulator quadbit. Ql of the modulator quadbit is a data ZERO for each signal element

21、. Signal elements are determined in accordance with 4.2.1. above. Figure 2/V.29 shows the absolute phase diagram of the transmitted signal elements at 7,200 bits per second. Relative signal I Qi I element amplitude I Absolute phase O“, go“, 180“, 270 - O 1 45“, 135“, 225“, 315“ Table 2/V.29. Figure

22、1/V.29 shows the absolute phase diagram of transmitted signal elements at 9,600 bits per second. At the fallback rate of 4,800 bits per second (see Table 3/V.29), the scrambled data stream to be transmitted is divided into groups of two consecutive data bits. The first data bit in time determines 42

23、 of the modulator quadbit and the second data bit determines 43 of the modulator quadbit. QI of the modulator quadbit is a data ZERO for each signal element. 44 is determined by inverting the modulo 2 sum of 42 + 43. The signal element is then determined in accordance with 4.2.1. above. Figure 3/V.2

24、9 shows the absolute phase diagram of transmitted signal elements at 4,800 bits per second. 4.2.3. Edition of November 30, 1985 CEPT T/CD*OI-Ob*E 79 2326434 0003IO I W O0 o1 11 10 T/CD 01-06 E Page 7 o O O 1 O o O 1 O 90“ o 1 1 1 180“ o 1 O O 270 Quadbitis QI 02 Q3 Q4 Phase change Data bit/s Table 3

25、lV.29. 4.3. Receiver 4.3.1. Received signal frequency tolerance The carrier frequency tolerance allowance at the transmitter is k 1 Hz. Assuming a maximum frequency drift of +6 Hz in the connection between the modems, the receiver must be capable of accepting errors of at least IT7 Hz in the receive

26、d signal frequency. 1800 Absolute t 270 Figure 1lV.29. Signal space diagram at 9,600 bit/s. 2700 Figure 21V.29. Signal space diagram at 7,200 bitls Edition of November 30, 1985 Absolute 90 Figure 3lV.29. Signal space diagram at 4,800 bitls. CEPT T/CD*OL-Ob*E = 232b4L4 0003LO 3 M Type of line signal

27、Number of symbol intervals Approximate time in ms* T/CD O1 -06 E Page 8 Total of Segment 1 Segment 2 Segment 3 Segment 4 segments 1, 2, 3 and 4 No transmitted Alternations conditioning all binary synchronizing 48 128 384 48 608 20 53 160 20 253 Equalizer Scrambled Total ONES signal energy pattern 4.

28、4. 4.4.1. 4.4.2. Egualizing requirements An automatic adaptive equalizer shall be provided in the receiver The receiver shall incorporate a means for detecting loss of equalization and initiating a synchronizing signal sequence in its associated local transmitter. The receiver shall incorporate a me

29、ans for detecting a synchronizing signal sequence from the remote transmitter and initiating a synchronizing signal sequence in its associated local transmitter, which may be initiated at any time during the reception of the synchronizing signal sequence, regardless of the state of circuit 105. Eith

30、er modem of a full-duplex connection can initiate the synchronizing signal sequence. The synchronizing signal is initiated when the receiver has detected a loss of equalization or when circuit 105 OFF to ON transition occurs in the carrier controlled mode, as described in 3.8.3. above. Having initia

31、ted a synchroniz- ing signal, the modem expects a synchronizing signal from the remote transmitter. If the modem does not receive a synchronizing signal from the remote transmitter within a time interval equal to the maximum expected two-way propagation delay, it transmits another synchronizing sign

32、al. A time interval of 1.2 s is recommended. If the modem fails to synchronize on the received signal sequence, it transmits another synchronizing signal. If a modem receives a synchronizing signal when it has not initiated a synchronizing signal and the receiver synchronizes properly, it returns on

33、ly one synchronizing sequence. Synchronizing Transmission of synchronizing signals may be initiated by the modem or by the associated data terminal equipment. When circuit 105 is used to control the transmitter carrier, the synchronizing signals are generated during the interval between the OFF to O

34、N transition of circuit 105 and the OFF to ON transition of circuit 106. When the receiving mode detects a circuit condition which requires resynchronizing, it shall turn circuit 106 OFF and generate a synchronizing signal. The synchronizing signals for all data rates are divided into four segments

35、as in Table 5/V.29. * Approximate times are provided for information only. The segment duration is determined by the exact number of symbol intervals. Table 5iV.29. Segment 2 of the synchronizing signal consists of alternations between two signal elements. The first signal element (A) transmitted ha

36、s a relative amplitude of 3 and defines the absolute phase reference of 180“. The second signal element (B) transmitted depends on the data rate. Figure 4/V.29 shows the B signal element at each of the data rates. Segment 2 alternates ABAB . ABAB for 128 symbol intervals. Segment 3 of the synchroniz

37、ing signals transmits two signal elements according to an equalizer conditioning pattern. The first signal element (C) has a relative amplitude of 3 and absolute phase of O“. The second signal element (D) transmitted depends on the data rate. Figure 4/V.29 shows the D signal element at each of the d

38、ata rates. The equalizer conditioning pattern is a pseudo-random sequence generated by the polynomial. Each time the pseudo-random sequence contains a ZERO, point C is transmitted. Each time the pseudo- random sequence contains a ONE, point D is transmitted. Segment 3 begins with the sequence CDCDCD

39、C . according to the pseudo-random sequence and continues for 384 symbol intervals. The detailed pseudo-random sequence generation is described in Appendix I. Edition of November 30, 1985 CEPT T/CD*OL-Ob*E 79 m 2326414 0003110 T m Segment 4 commences transmission according to the encoding described

40、in 4.2. above with cor T/CD O1 -06 E Page 9 t D(9600) D(4OO) t 00 Absolute B (7200) t Figure 4/V.29. Signal space diagram showing synchronizing signal points. inuous da 1 ONES applied to the input of the data scrambler. Segment 4 duration is 48 symbol intervals. At the end of segment 4, circuit 106

41、is turned ON and user data are applied to the input of the data scrambler. Response time for circiiit 106 The time between the OFF to ON transition of circuit 105 and the OFF to ON transition of circuit 106 shall be optionally 15 ms15 ms or 253.5 msk0.5 ms. 4.4.3. O The short delay is used when circ

42、uit 105 does not control the transmitter carrier. The long delay is used when circuit 105 controls the transmitter carrier and a synchronizing signal is initiated by the OFF to ON transition of circuit 105. The time between the ON to OFF transition of circuit 105 and the ON to OFF transition of circ

43、uit 106 shall be suitably chosen to ensure that all valid signal elements have been transmitted. 5. SCRAMBLING A seif-synchronizing scrambler/descrambler having the generating polynomial 1 + x-* + x- shall be included in the modem. At the transmitter the scrambler shall effectively divide the messag

44、e polynomial, of which the input data sequence represents the coefficients in descending order, by the scrambler generating polynomial to generate the transmitted sequence. At the receiver the received polynomial, of which the received data sequence represents the coefficients in descending order, s

45、hall be multiplied by the scrambler generating polynomial to recover the message sequence. The message polynomial is divided by the generating polynomial I + x- + x- (see Figure 6/V.29). The coefficients of the quotient of this division taken in descending order form the data sequence to be transmit

46、ted. In order to ensure that proper starting sequence is generated, the shift register is fed with “0” during segments 1, 2 and 3. During segment 4 and normal data transmission it is fed with scrambled data D, (input data Di being “1” during segment 4). D, = Di + D,b* + D,x- 5.1. Descrambling The po

47、lynomial represented by the received sequence is multiplied by the generating polynomial (Figure 7/V.29) to form the recovered message polynomial. The Coefficients of the recovered polynomial, taken in descending order, form the output data sequence Do. Do = Di = D, (1 + X-” + x-) Edition of Novembe

48、r 30, 1985 CEPT T/CD*OL-Ob*E M 2326414 0003LLL II T/CD O1 -06 E Page 1 O 0, x-8 v o, x-23 Figure 7lV.29. 5.1.1. 6. 7. 8. 8.1. 8.2. 8.2.1. 8.2.2. Elements of the scrambling process The polynomial 1 + x-I8 + x-23 generates a pseudo-random sequence of length 223 -1 = 8,388,607. This long sequence does

49、not require the use of a guard polynomial to prevent the occurrence of repeat patterns and is particularly simple to implement with integrated circuits. TIMING Clocks should be included in the modem to provide the data terminal equipment with transmitter signal element timing (Recommendation V.24, circuit 1 14) and receiver signal element timing (Recommendation V.24, circuit 115). In this arrangement, the transmitter may either run as an independent timing source or with loopback timing. Loopback timing may be desirable in some network applications. Alterna