Intermediate x86Part 4.ppt

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1、Intermediate x86 Part 4,Xeno Kovah 2010 xkovah at gmail,All materials are licensed under a Creative Commons “Share Alike” license.,http:/creativecommons.org/licenses/by-sa/3.0/,2,3,Interrupts & Debugging,We know that IDT3 is the Breakpoint Exception, and that its important enough for INT 3 to have a

2、 separate one byte opcode form (0xCC). INT 3 is what debuggers are using when they say they are setting a “software breakpoint” (the default breakpoint in most cases) When a debugger uses a software breakpoint, what it does is overwrite the first byte of the instruction at the specified address. It

3、keeps its own list of which bytes it overwrote and where. Then when breakpoint exception is received, it looks up the location, replaces the original byte and lets the instruction execute normally. Then typically it overwrites the first byte again (subject to configuration) so that the breakpoint wi

4、ll be hit if the address is executed again.,Lab: ProofPudding.c,A program which reads its own memory in order to confirm that when a breakpoint is set, it overwrites a byte with the 0xCC form of the breakpoint interrupt, INT 3,4,5,Hardware Support for Debugging,Most debuggers also have support for s

5、omething called a “hardware breakpoint”, and these breakpoints are more flexible than software breakpoints in that they can be set to trigger when memory is read or written, not just when its executed. However only 4 hardware breakpoints can be set. There are 8 debug registers DR0-DR7 DR0-3 = breakp

6、oint linear address registers DR4-5 = reserved (unused) DR6 = Debug Status Register DR7 = Debug Control Register Accessing the registers requires CPL = 0 MOV DR, r32 MOV r32, DR,Vol. 3b, Sect. 18,6,Picture This,7,DR7 - Debug Control Register,L0-3 (local breakpoint enable) flags - Enables the DR0-3 b

7、reakpoint. But these flags are cleared on task switches to ensure that they do not fire when dealing with a different task. G0-3 (global breakpoint enable) flags - Enables the DR0-3 breakpoint. Does not get cleared on task switch, which is what makes it global obviously. LE & GE (local and global ex

8、act breakpoint enable) flags - If set to 1, enables detection of the exact instruction that caused a data breakpoint. Not supported on P6 microarchitecture and later, but if you need maximum compatibility for exact breakpoint detection youre recommended to set both to 1.,8,DR7 - Debug Control Regist

9、er (2),GD (General Detect) flag - If set to 1, causes a debug exception prior to MOV instructions which access the debug registers. The flag is cleared when the actual exception occurs though, so that the handler can access the debug register as needed. The R/W0-3 are interpreted as follows: 00 = Br

10、eak on instruction execution only. 01 = Break on data writes only. If(CR4.DE = 1) then 10 = Break on I/O reads or writes. If(CR4.DE = 0) then 10 = Undefined. 11 = Break on data reads or writes but not instruction fetches.,9,DR7 - Debug Control Register (3),LEN0-4 bits specify what size the address s

11、tored in the DR0-3 registers should be treated as. 00 = 1-byte 01 = 2-bytes 10 = Undefined (or 8 bytes, see note below) 11 = 4-bytes. While you might set a 1 byte size for an address pointing at the first byte of an instruction, on a break-on-execute, you might want to set a 4 byte breakpoint on wri

12、tes to a memory location you know to be a DWORD. “For Pentium 4 and Intel Xeon processors with a CPUID signature corresponding to family 15 (model 3, 4, and 6), break point conditions permit specifying 8-byte length on data read/write with an of encoding 10B in the LENx field.”,10,DR6 - Debug Status

13、 Register,B0-B3 (breakpoint condition detected) flags - When the B0,1,2,3 bit is set, it means that the 0th,1st,2nd,3rd condition specified in DR7 has been satisfied. The bits are set even if the DR7 says that condition is currently disabled. I.e. software needs to crosscheck these bits against whet

14、her it currently cares. BD (debug register access detected) flag - Indicates that the next instruction will try to access the debug registers. This flag only enabled if GD (general detect) flag in DR7 is set. Thus this signals if someone else was trying to access the debug registers. NO! MINE!,11,DR

15、6 - Debug Status Register (2),BS (single step) flag - If set, the debug exception was triggered by single-step execution mode (talked about later). BT (task switch) flag - Related to TSS so we dont care “Certain debug exceptions may clear bits 0-3. The remaining contents of the DR6 register are neve

16、r cleared by the processor. To avoid confusion in identifying debug exceptions, debug handlers should clear the register before returning to the interrupted task.” Seems like an important point if youre making a debugger :),12,So what actually happens when a hardware breakpoint fires?,It fires IDT1,

17、 a Debug Exception When it is an execute breakpoint or general detect (someone trying to access debug regs) its a fault. For other cases Its A Trap!That means if it was a break on write, the data is overwritten before the exception is generated. A handler which wants to show the before and after is

18、responsible for keeping a copy of the before value. Instruction breakpoints are actually detected before the instruction executes. Therefore if the handler doesnt remove the breakpoint, and it just returned, the same exception would be raised over and over. This is where the Resume Flag (RF) comes i

19、nto play,13,Resume Flag (RF in EFLAGS),When the RF is set, the processor ignores instruction breakpoints. To set the flag, a debug interrupt handler would manipulate the EFLAGS stored on the stack and then use IRETD (POPF, POPFD, and IRET do not transfer RF from the stack into EFLAGS) “The processor

20、 then ignores instruction breakpoints for the duration of the next instruction.” “The processor then automatically clears this flag after the instruction returned to has been successfully executed.”,14,Trap Flag (TF in EFLAGS),Only being able to invoke the debug exception handler on 4 addresses is s

21、omewhat limiting. When TF is 1, it causes a debug exception after every instruction. This is called “single-step” mode. Useful for capabilities such as “step out” which just steps until it steps through a RET Remember that we said that if the debug exception is in response to single stepping, it set

22、s the BS flag in DR6. The processor clears the TF flag before calling the exception handler, so if it wants to keep single-stepping it needs to set it again before returning. Also, the INT and INTO instructions clear TF. So a single stepping debugger handler should compensate accordingly.,WinDbg Har

23、dware Breakpoints,Hardware Breakpoint = ba rather than bp. Stands for break on access, where access can be read/write/execute or port IO. Below is a simplified form of the command (see help page for full form) ba Access Size Address Access r = read/write w = write e = execute i = I/O port (talked ab

24、out later) Size. Width of data over which you want the breakpoint to have effect. Must be 1 for access = e, but can be 1, 2, 4, or 8 for other types Address. Where you want the breakpoint to be targeted.,15,HW Breakpoint Examples,ba e 1 0x80541ac0 Break on execute of address 0x80541ac0 (windbg speci

25、fies size must be 1 on break on execute) ba w 4 0x80541ac0 Break if anyone reads from the 4 bytes specified by 0x80541ac0 to 0x80541ac4 ba r 2 0x80541ac0 Break if anyone reads or writes from byte 0x80541ac0 or 0x80541ac1(remember, the debug registers dont have a way to specify only read),16,17,Lab:

26、Watching the debugger debug,TryToRunTryToHide.c take 2 A discourse on the efficacy of using a hardware breakpoint on the INT 3 handler, rather than a software breakpoint ;),18,Malware Use of Debug Regs,“A packer such as tElock makes use of the debug registers to prevent reverse-engineers from using

27、them. “ http:/ The Art of Unpacking (lists various anti-debug tricks including reading the debug registers) https:/ But I thought you had to be running in ring 0 to manipulate debug registers? Well, yes, but windows saves thread information (including the contents of the debug register) into a CONTE

28、XT structure, and provides userspace a way to get and set thread context, thus letting malware detect .,19,The New Stuff (Which I dont yet know enough about to teach. Read 3b, Sect. 18.4 on your own),“P6 family processors introduced the ability to set breakpoints on taken branches, interrupts, and e

29、xceptions, and to single-step from one branch to the next. This capability has been modified and extended in the Pentium 4, Intel Xeon, Pentium M, Intel CoreTM Solo, Intel CoreTM Duo, Intel CoreTM2 Duo, Intel CoreTM i7 and Intel AtomTM processors to allow logging of branch trace messages in a branch

30、 trace store (BTS) buffer in memory.” The branch trace is basically a stack which holds pairs of addresses which represent the source of the branch and the destination. Pedram Amini talked about the performance improvement vs. single step mode here: http:/www.openrce.org/blog/view/535/Branch_Tracing

31、_with_Intel_MSR_Registers,20,Port I/O,“In addition to transferring data to and from external memory, IA-32 processors can also transfer data to and from input/output ports (I/O ports).” “I/O ports are created in system hardware by circuity that decodes the control, data, and address pins on the proc

32、essor. These I/O ports are then configured to communicate with peripheral devices.” “An I/O port can be an input port, an output port, or a bidirectional port.”,Vol 1, Sect 13,21,Ports,There are 216 8bit IO ports, numbered 0-0xFFFF. Can combine 2 or 4 consecutive ports to achieve a 16 or 32 bit port

33、. “32-bit ports should be aligned to addresses that are multiples of four (0, 4, 8, .).”,22,Accessing the Ports,You cannot use the IN/OUT instructions to access the ports unless you have sufficient privileges. There is a 2 bit IOPL (I/O Privilege Level) field in EFLAGS. You can only perform IO if CP

34、L = IOPL. Also FYI, the STI/CLI instructions we saw before also are only allowed if CPL = IOPL. Most OSes set IOPL to 0 But think back to privilege rings. An appropriately modified OS (say, a paravirtualized one), could allow IOPL to be something like 2.,23,IN - Input from Port,Note its DX, not DL.

35、That means the DX form can specify all 216 ports, but the IMM8 form can only specify 28 ports. “When accessing a 16- and 32-bit I/O port, the operand-size attribute determines the port size.” (Because as usual theres an overloaded opcode for 16/32 bit form) Remember if youre in a 16 bit segment its

36、16 bit, if youre in a 32 bit segment its 32 bit. But you can override it with an operand size instruction prefix which is talked about later.,24,OUT - Output to Port,Basically the same caveat as IN,Lab: ParlorTrick.c,Accessing the vmware “backdoor” IO port. For more tricks, see VMBack - http:/chitch

37、at.at.infoseek.co.jp/vmware/backdoor.html,25,The 8042 keyboard controller,Lots of good info here: http:/puter-engineering.org/ps2keyboard/ The original IBM PC used a chip by the name of 8042 as the keyboard controller. PS/2 keyboards use this chip, and luckily for us, so do VMWare virtual machines b

38、y default (since PS/2 is way simpler than USB) The 8042 has a status/command register mapped to IO port 0x60 and a data register mapped to IO port 0x64,26,Lab: basic_hardware.c Spooky action at a distance,Code taken as-is from http:/ Starts a timer in the kernel which calls a function every 300ms. T

39、hat function talks to the keyboard controller using port IO, and sets a new value for the LED indicator lights for Num/Caps/Scroll lock,27,Lab: bhwin_keysniff.c Low level keystroke logging,Code taken from http:/ with changes and hackery to get it to work as noted inline Every time a key is pressed/r

40、eleased, it triggers an interrupt. In our case it is INT0x93 which is usually handled by i8042prt.syss I8042KeyboardInterruptService() function. Keys are represented as “scancodes” indicating position on the keyboard, not ASCII values. This code hooks the keyboard interrupt( i.e. puts itself into th

41、e IDT descriptor) and then reads and stores the incoming scancode, puts it back into the buffer, and then calls the original handler.,28,HW Breakpoint Examples,WinDbg commands to set a breakpoint on port IO ba i 1 0x60 Break on 1 byte access to port address 0x60 The value read in will be in al ba i

42、4 0x60 Break on 1-4 byte access to port address 0x60 The value read in will be in al, ax, or eax depending on the size used in the IN instruction,29,Debug Reg Keyboard Sniffer,We just saw from the bhwin_keysniff.c source, that you speak to port 0x60 to talk to the 8042 keyboard controller. We saw ea

43、rlier that the debug registers have an option to break on port IO access. Combine, and you get a keyboard sniffer which hooks the debug breakpoint handler rather than keyboard handler (but still has to hook the IDT to catch the debug register interrupts, INT 1). It is admittedly fragile. If someone

44、overwrites the debug reg entry, purposely or accidentally, it is blinded. But it could keep polling to check if it has been removed, and replace itself. Though sooner or later an analyst is going to wonder why his hardware breakpoints keep getting missed and overwritten. PoC: http:/ the future (valu

45、es of registers)! Impress friends and cow orkers! Be the life of the party! Burn excess calories! Live in infamy! Call Now! Just 9 easy payments of 9.99!,31,Tap Into Your Hidden Potential and Disassemble Binary Using Only THE POWER OF YOUR MIND!,(Dramatic) Intel Instruction Format,32,“r/m32”,33,Expl

46、aination of “r/m32s”,What I called an “r/m32” is actually the combination of the “ModR/M” and “SIB” bytes from the previous slide I had previously promised to get into why AND has a /4 in its opcode column. Vol. 2a page 3-2 section 3.1.1.1s explanation of the opcode column says: “/digit - A digit be

47、tween 0 and 7 indicates that the ModR/M byte of the instruction uses only the r/m (register or memory) operand. The reg field contains the digit that provides an extension to the instructions opcode.” “/r Indicates that the ModR/M byte of the instruction contains a register” operand and an r/m opera

48、nd. And heres what 3.1.1.2 says about the instruction column: OK, whats a “ModR/M” byte?,34,The src/dst register part,The memory part,35,This is misleading. Looking at the chart you would think you cant access ESP, but you can (if your instruction either uses /r (or /5? Any such instruction?),The ba

49、se register,36,Examples of testing,(You have to put each _emit on its own line, I just wrote them this way for conciseness) _asm_emit 0x80; _emit 0x20; _emit 0xFF; 80 20 FF and byte ptr eax,0FFh _asm_emit 0x80; _emit 0x60; _emit 0x20; _emit 0xFF; 80 60 20 FF and byte ptr eax+20h,0FFh _asm_emit 0x80; _emit 0x00; _emit 0xFF; 80 00 FF add byte ptr eax,0FFh Wait, add? But Im still using 0x80 at the front?!,