A New DMA Registration Strategyfor Pinning-Based High .ppt
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1、A New DMA Registration Strategy for Pinning-Based High Performance Networks,Dan Bonachea & Christian Bell U.C. Berkeley and LBNL bonachea,csbellcs.berkeley.edu http:/www.cs.berkeley.edu/bonachea/gasnet,This work is part of the UPC and Titanium projects, funded in part by the DOE, NSF and DOD,Problem
2、 Motivation: Client,Global-address space (GAS) languages UPC, Titanium, Co-Array Fortran, etc. Large globally-shared memory areas w/language support for direct access to remote memory Total remotely accessible memory size limited only by VM space Working set of memory being touched likely to fit in
3、physical mem App performance tends to be sensitive to the latency & CPU overhead for small operations Implications for communication layer (GASNet) Want low-latency and low-overhead for non-blocking small puts/gets (think 8 bytes) Want high-bandwidth, zero-copy msgs for large transfers zero-copy: ge
4、t higher bandwidth AND avoid CPU overheads Ideally all communication should be fully one-sided one-sided: dont interrupt remote host CPU - hurts remote compute performance and increases round-trip latency,Problem Motivation: Hardware,Pinning-based NICs (e.g. Myrinet, Infiniband) Provide one-sided RD
5、MA transfer support, but Memory must be explicitly registered ahead of time Requires explicit action by the host CPU on both sides Tell the OS to pin virtual memory page (kernel call) Register fixed virtual/physical mapping w/NIC (PCI transaction) Memory registration can be expensive! Especially on
6、Myrinet - average is 40 microsec to register one page, 6 milliseconds to deregister one page Costs primarily due to preventing race conditions with pending messages that could compromise system memory protection Want to reduce the frequency of registration operations and the need for two-sided synch
7、ronization Reducing cost of a single registration operation is also important, but orthogonal to this research,Memory Registration Approaches,Hardware-Based (e.g. Quadrics) Zero-copy, One-sided, Full memory space accessible, No handshaking or bookkeeping in software Hardware complexity and price, Ke
8、rnel modifications Pin Everything - pin pages at startup or when allocated Zero-copy, One-sided (no handshaking) Total usage limited physical memory, may require a custom allocator Bounce Buffers - stream data through pre-pinned bufs No registration cost at runtime, Full memory space accessible Two-
9、sided, mem copy costs (CPU consumption - increases CPU overhead, prevents comm. overlap), Messaging overhead (metadata and handshaking) Rendezvous - round-trip message to pin remote pages Zero-copy, Full memory space accessible, Only handshaking synchronous Two-sided, Registration costs paid on ever
10、y operation (very bad on Myrinet) Firehose - our algorithm Zero-copy, One-sided (common case), Full memory space accessible, Only handshaking is synchronous, Registration costs amortized Messaging overhead (metadata and handshaking) on miss (uncommon case),Basic Idea: A Hybrid Approach,Firehose - A
11、distributed strategy for handling registration Get the benefits of Pin-Everything in the common case Revert to Rendezvous-like behavior for the uncommon case Allow remote nodes to control and cache registration ops Each node sets aside M bytes of physical memory for registration purposes (some reaso
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