JEDEC JESD209B-2010 Low Power Double Data Rate (LPDDR) SDRAM Standard.pdf

《JEDEC JESD209B-2010 Low Power Double Data Rate (LPDDR) SDRAM Standard.pdf》由会员分享，可在线阅读，更多相关《JEDEC JESD209B-2010 Low Power Double Data Rate (LPDDR) SDRAM Standard.pdf（76页珍藏版）》请在麦多课文档分享上搜索。

1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD209BFEBRUARY 2010JEDECSTANDARDLow Power Double Data Rate (LPDDR) SDRAM Standard(Revision of JESD209A, February 2009)SPECIAL DISCLAIMER: JEDEC has received information that certain patents or patent applications may be essential to this standard. However, a

2、s of the publication date of this standard, no statements regarding an assurance or refusal to license such patents or patent applications have been provided. Contact JEDEC for further information. JEDEC does not make any determination as to the validity or relevancy of such patents or patent applic

3、ations. Anyone making use of the standard assumes all liability resulting from such use. JEDEC disclaims any representation or warranty, express or implied, relating to the standard and its use.NOTICEJEDEC standards and publications contain material that has been prepared, reviewed, and approved thr

4、ough the JEDEC Council level and subsequently reviewed and approved by the EIA General Counsel.JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of pro

5、ducts, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally.JEDEC standards and publications are adopted without regard to whether or not their

6、 adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications.The information included in JEDEC standards and publications

7、represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met.Inquiries, comments, and suggestions relative to

8、the content of this JEDEC standard or publication should be addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard, Arlington, VA 22201-3834, (703)907-7559 or www.jedec.org.Published byJEDEC Solid State Technology Association 20072500 Wilson BoulevardArlington, VA 22201-3834Thi

9、s document may be downloaded free of charge, however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material.Price: Please refer to the current Catalog of JEDEC Engineering Standards and Publications or www.jedec

10、.org.Documents, USA and Canada (1-800-854-7179), International (303-397-7956)Printed in the U.S.A.All rights reservedPLEASE!DONT VIOLATETHELAW!This document is copyrighted by the JEDEC Solid State Technology Associationand may not bereproduced without permission.Organizations may obtain permission t

11、o reproduce a limited number of copies through entering into a license agreement. For information, contact:JEDEC Solid State Technology Association3103 North 10th Street, Suite 240 SouthArlington, Virginia 22201-2107or call (703) 907-7559Special Disclaimer JEDEC has received information that certain

12、 patents or patent applications may be essential to this standard. However, as of the publication date of this standard, no statements regarding an assurance or refusal to license such patents or patent applications have been provided. Contact JEDEC for further information. JEDEC does not make any d

13、etermination as to the validity or relevancy of such patents or patent applications. Anyone making use of the standard assumes all liability resulting from such use. JEDEC disclaims any representation or warranty, express or implied, relating to the standard and its use.JEDEC Standard No. 209BConten

14、ts1 Scope 12 Low-Power Double Data Rate (LPDDR) SDRAM Devices .22.1 Features 22.2 General Description .22.2.1 Packages42.3 Terminology and Definitions.93 Functional Description103.1 Initialization 103.1.0.1 TQ Signal Initialization .133.2 Register Definition.133.2.1 Mode Register 133.2.1.1 Burst Len

15、gth 143.2.1.2 Burst Type .163.2.1.3 Read Latency .163.2.2 Extended Mode Register 163.2.2.1 Partial Array Self Refresh (Optional) .173.2.2.2 Temperature Compensated Self Refresh (Optional) .173.2.2.3 Output Drive Strength .173.2.3 Status Register Read (Optional)183.2.4 Temperature Output Signal (opti

16、onal) 204 Commands 215 Operation.265.1 Deselect .265.2 No Operation .265.3 Mode Register Set .265.4 Active 275.5 Read 285.5.1 Read to Read 305.5.2 Read Burst Terminate 305.5.3 Read to Write .305.5.4 Read to Precharge 305.5.5 Burst Terminate 345.6 Write 345.6.1 Write to Write 375.6.2 Write to Read .3

17、75.6.3 Write to Precharge: 375.7 Precharge .415.8 Auto Precharge 425.9 Refresh Requirements .425.10 Auto Refresh .425.11 Self Refresh 42-i-JEDEC Standard No. 209BContents5.12 Power-Down .445.13 Deep Power-Down 455.14 Clock Stop .466 Absolute Maximum Ratings .487 AC Figure 4 and Figure 51563.01 JC-42

18、.3-04-038 LPDDR Deep Power Down mode pp 45 and Figure 421604.01 JC-42.3-04-150A LPDDR IV Curve Table 17, Figure 45 and Figure 471625.03 JC-42.3-04-392 LPDDR over/undershoot Table 16 and Figure 441718.05 JC-42.6-07-357 LPDDR400 SDRAM AC Parameters Table 141718.08 JC-42.6-07-358 LPDDR400 SDRAM TQ Pad

19、ProposalTable 3, Figure 5, description page 20, Table 141718.13 JC-42.6-07-264LPDDR SDRAM 60-, 90-Ball BGA Ballouts with A13 ball Figure 21718.14 JC-42.6-07-265LPDDR SDRAM 60-, 90-Ball BGA Ballouts with additional CS#, CKE Figure 1 and Figure 21718.15 JC-42-6.07-359LPDDR SDRAM Output Driver Characte

20、ristics Figure 7, Table 15, Table 17, Table 18, and Figure 46.1718.16 JC-42.6-07-360 LPDDR SDRAM address tables Table 21723.02 JC-42.6-08-255LPDDR SDRAM 1.2V Output CharacteristicsLPDDR SDRAM 1.2V I/O Addendum1718.18 JC-42.6-08-331 LPDDR tRC two data transfers per clock cycle Bidirectional, data str

21、obe (DQS) is transmitted/received with data, to be used in capturing data at the receiver Differential clock inputs (CK and CK) Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS Four internal banks for concurrent operation Data mask (DM) for write data Bur

22、st Length: 2, 4 or 8 (16 is optional) Burst Type: Sequential or Interleave CAS latency: 3 (2 accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ o

23、r WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access.The LPDDR SD

24、RAM provides for programmable read or write bursts of 2, 4 or 8 locations. Some vendors may offer an optional burst length of 16. An Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.As with standard SDRAMs, the pipelined, m

25、ultibank architecture of LPDDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation times.An Auto Refresh mode is provided, along with a power saving Power-down mode. Self Refresh mode may have Temperature Compensated Self Refresh

26、(TCSR) and Partial Array Self Refresh (PASR) options, which allow users to achieve additional power saving. The TCSR and PASR options can be programmed via the extended mode register.All inputs are LV-CMOS compatible. Devices will have a VDD and VDDQ supply of 1.8 V (nominal).This datasheet includes

27、 all features and functionality required for JEDEC LPDDR SDRAM devices. Certain vendors may elect to offer a superset of this specification by offering improved timings and/or including optional features. Users benefit from knowing that any system design based on the required aspects of the specific

28、ation are supported by all LPDDR SDRAM vendors; conversely users seeking to use any superset specifications bear the responsibility to verify support with individual vendors.Table 2 LPDDR SDRAM Addressing TableItem 64 Mb 128 Mb 256 Mb 512 Mb 1 Gb 2 GbNumber of banks 4 4 4 4 4 4Bank Address Pins BA0,

29、 BA1 BA0, BA1 BA0, BA1 BA0, BA1 BA0, BA1 BA0, BA1Autoprecharge Pin A10/AP A10/AP A10/AP A10/AP A10/AP A10/APx16Row Addresses A0-A11 A0-A11 A0-A12 A0-A12 A0-A13 A0-A13Column Addresses A0-A7 A0-A8 A0-A8 A0-A9 A0-A9 A0-A9, A11tREFI(s) 15.6 15.6 7.8 7.8 7.8 7.8x32Row Addresses A0-A10 A0-A11 A0-A11 A0-A1

30、2 A0-A12 A0-A13 A0-A13Column Addresses A0-A7 A0-A7 A0-A8 A0-A8 A0-A9 A0-A8 A0-A9tREFI(s) 15.6 15.6 15.6 7.8 7.8 7.82 Low-Power Double Data Rate (LPDDR) SDRAM Devices (contd)2.2 General Description (contd)JEDEC Standard No. 209BPage 42.2.1 PackagesSingle-die, one CS# and one CKE:In the 60-ball x16 pa

31、ckage,a maximum SDRAM density of 2Gb can be achieved only with 2-KByte page size and most significant address bit A13.In the 90-ball x32 package, a maximum SDRAM density of 2Gb can be achieved either with 2-KByte page size and most significant address bit A13, or with 4-KByte page size and most sign

32、ificant address bit A12.Dual-die, two CS# and two CKE:In the 60-ball x16 package, a maximum SDRAM density of 1Gb can be achieved with most significant address bit A12.In the 90-ball x32 package, a maximum SDRAM density of 2Gb can be achieved with most significant address bit A12.Figure 1 Pin Configu

33、ration of x16 LPDDR SDRAM IN BGA60-Ball (6x10) CSP1 2 3 7 8 9A VSS DQ15 VSSQ VDDQ DQ0 VDDB VDDQ DQ13 DQ14 DQ1 DQ2 VSSQC VSSQ DQ11 DQ12 DQ3 DQ4 VDDQD VDDQ DQ9 DQ10 DQ5 DQ6 VSSQE VSSQ UDQS DQ8 DQ7 LDQS VDDQF VSS UDM NC,CKE1 A13,NC,CS1 LDM VDDG CKE0 CK CK WE CAS RASH A9 A11 A12,NC CS0 BA0 BA1J A6 A7 A8

34、 A10/AP A0 A1K VSS A4 A5 A2 A3 VDDFEDCBJHGAK47936512 8Top View(Balls seen through the package)2 Low-Power Double Data Rate (LPDDR) SDRAM Devices (contd)2.2 General Description (contd)JEDEC Standard No. 209BPage 5Figure 2 Pin Configuration of x32 LPDDR SDRAM IN BGAFEDCBJHGAK47936512 8Top View(Balls s

35、een through the package)LPNMR90-Ball (6x15) CSP1 2 3 7 8 9A VSS DQ31 VSSQ VDDQ DQ16 VDDB VDDQ DQ29 DQ30 DQ17 DQ18 VSSQC VSSQ DQ27 DQ28 DQ19 DQ20 VDDQD VDDQ DQ25 DQ26 DQ21 DQ22 VSSQE VSSQ DQS3 DQ24 DQ23 DQS2 VDDQF VDD DM3 NC,CKE1 A13,NC,CS1 DM2 VSSG CKE0 CK CK WE CAS RASH A9 A11 A12,NC CS0 BA0 BA1J A

36、6 A7 A8 A10/AP A0 A1K A4 DM1 A5 A2 DM0 A3L VSSQ DQS1 DQ8 DQ7 DQS0 VDDQM VDDQ DQ9 DQ10 DQ5 DQ6 VSSQN VSSQ DQ11 DQ12 DQ3 DQ4 VDDQP VDDQ DQ13 DQ14 DQ1 DQ2 VSSQR VSS DQ15 VSSQ VDDQ DQ0 VDD2 Low-Power Double Data Rate (LPDDR) SDRAM Devices (contd)2.2 General Description (contd)JEDEC Standard No. 209BPage

37、 6Table 3 Pin DescriptionsSymbol Type DescriptionCK, CK InputClock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Input and output data is referenced to the crossing of CK and CK (both di

38、rections of crossing). Internal clock signals are derived from CK/CK.CKE InputClock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or AC

39、TIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for all functions except for SELF REFRESH EXIT, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE, are disabled during power-down and self refresh mode which are contrived for low standby power consumption. CS Input

40、Chip Select: CS enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code.RAS, CAS, WEInputCommand Inputs: RAS, CAS

41、 and WE (along with CS) define the command being entered.DMfor x16: LDM, UDMfor x32: DM0-DM3InputInput Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM

42、pins are input-only, the DM loading matches the DQ and DQS loading.For x16 devices, LDM corresponds to the data on DQ0-DQ7, UDM corresponds to the data on DQ8-DQ15.For x32 devices, DM0 corresponds to the data on DQ0-DQ7, DM1 corresponds to the data on DQ8-DQ15, DM2 corresponds to the data on DQ16-DQ

43、23, and DM3 corresponds to the data on DQ24-DQ31.BA0, BA1 InputBank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. A n : 0 InputAddress Inputs: provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit f

44、or READ / WRITE commands, to select one location out of the memory array in the respective bank. The address inputs also provide the opcode during a MODE REGISTER SET command.DQ for x16: DQ0-DQ15for x32: DQ0-DQ31I/O Data Bus: Input / OutputDQSfor x16: LDQS,UDDSfor x32:DQS0-DQS3I/OData Strobe: Output

45、 with read data, input with write data. Edge-aligned with read data, centered with write data. Used to capture write data.For x16 device, LDQS corresponds to the data on DQ0-DQ7, UDQS corresponds to the data on DQ8-DQ15.For x32 device, DQS0 corresponds to the data on DQ0-DQ7, DQS1 corresponds to the

46、 data on DQ8-DQ15, DQS2 corresponds to the data on DQ16-DQ23, and DQS3 corresponds to the data on DQ24-DQ31.NC No Connect: No internal electrical connection is presentVDDQ Supply I/O Power SupplyVSSQ Supply I/O GroundVDD Supply Power SupplyVSS Supply Ground2 Low-Power Double Data Rate (LPDDR) SDRAM

47、Devices (contd)2.2 General Description (contd)JEDEC Standard No. 209BPage 7TPD(Test Power Down)InputOptional pad, Test Power Down or TPD, for test purposes only. TPD LOW is normal operation. Taking TPD HIGH asynchronously will place the die in deep power down mode. The assertion of TPD HIGH must mee

48、t all the initialization and sequencing of DPD modeTQ OutputOptional. Asynchronous, LVCMOS temperature output. Output logic-HIGH state when device temperature equals or exceeds 85C. Output logic-LOW state when device temperature is less than 85C.Table 3 Pin DescriptionsSymbol Type Description2 Low-P

49、ower Double Data Rate (LPDDR) SDRAM Devices (contd)2.2 General Description (contd)JEDEC Standard No. 209BPage 8Figure 3 Simplified State DiagramPowerOnPo werappliedACTAutoRefreshAct ivePowerDownCKEHCKELWRITEWRITE AREADREADAWRITEAREADAWRITEAPREREADAPREAutomatic SequenceCommand SequenceREADACT = ActiveBST = Burst TerminateCKEL = Enter Power-DownCKEH = Exit Power-DownD PDS = Enter Dee p Po wer-Dow nD PDSX = Exit Deep Pow er- DownEMRS = Ext. Mode Reg. SetMRS = Mo de Register SetPRE = PrechargePREALL = Prech arge All BanksREFA = Au to RefreshREFS = En ter S