DLA SMD-5962-95824-1996 MICROCIRCUIT DIGITAL RADIATION HARDENED CMOS 8-BIT MICROPROCESSOR MONOLITHIC SILICON《抗辐射互补金属氧化物半导体8-BIT微处理器硅单片电路线型微电路》.pdf

《DLA SMD-5962-95824-1996 MICROCIRCUIT DIGITAL RADIATION HARDENED CMOS 8-BIT MICROPROCESSOR MONOLITHIC SILICON《抗辐射互补金属氧化物半导体8-BIT微处理器硅单片电路线型微电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-95824-1996 MICROCIRCUIT DIGITAL RADIATION HARDENED CMOS 8-BIT MICROPROCESSOR MONOLITHIC SILICON《抗辐射互补金属氧化物半导体8-BIT微处理器硅单片电路线型微电路》.pdf（25页珍藏版）》请在麦多课文档分享上搜索。

1、LTR REV STATUS I REV III DESCRIPTION DATE (YRMO-DA) APPROVED OF SHEETS SIZE A PREPARED BY Thomas M. Hess PMIC NIA 5962-95824 CAGE CODE 67268 CHECKED BY STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE APPROVED BY Monica L. P

2、oelking I I DRAWING APPROVAL DATE 96-01 -1 O AMSC NfA REVISION LEVEL DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 MICROCIRCUIT, DIGITAL, RADIATION HARDENED, SILICON CMOS, 8-BIT MICROPROCESSOR, MONOLITHIC SHEET 1 OF 24 I )ESC FORM 193 JUL 94 DISTRIBUTION STATEMENT A Approved for public releas

3、e, distribution is unlimited 5962-E220-96 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,- SMD-5762-95824 9999996 0082532 83T SIZE A STANDARD MICROCIRCUIT DRAWING DEFENSEELECTRONICSSUPPLYCENTER DAYTON, OHIO 45444 1. SCOPE 1.1 m. This drawing forms a

4、part of a one part - one part der docunentation system (see 6.6 herein). Two product assurance classes consisting of military high reliability (device classes P and M) and space application (device class V), and a choice of case outlines and lead finishes are available and are reflected in the Part

5、or Identifying Nunber (PIN). 1.2.1 of MIL-STD-883, anProvisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devicesaa. available, a choice of Radiation Hardness Assurance (RHAI levels are reflected in the PIN. Device class M microcircuits represent non-JAN class B microcircuits

6、in accordance with When 1.2 m. The PIN shall be as shown in the following example: TT-LLff Federal R HA Device Device Case Lead stock class designator type class out 1 ine finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) (see 1.2.3) / Drawing nunber 1.2.1 MA desisnator .

7、Device class M RHA marked devices shall meet the MIL-1-38535 appendix A specified RHA levels and shall be marked with the appropriate RHA designator. YIL-1-38535 specified RHA levels and shall be marked with the appropriate RHA designator. non-RHA device. Device classes Q and V RHA marked devices sh

8、all met the A dash (-1 indicates a 5962-95824 REVISION LEVEL SHEET 2 1.2.2 pevice tvDe(s1 . The device type(s) shall identify the circuit function as follows: mice tw Generic nunbec ircuit functiw o1 80C85RH Radiation Hardened, CMOS, 8-bit microprocessor 1.2.3 pevice c(a ss desisnato r. The device c

9、lass designator shall be a single letter identifying the product assurance level as follows: Pevice class Device reauirements docmentation M Vendor self-certification to the requirements for non-JAN class B microcircuits in accordance with 1.2.1 of MIL-STD-883 P or V Certification and qualification

10、to MIL-1-38535 1.2.4 Case outliw . The case outline(s) shall be as designated in MIL-STD-1835 and as follows: pyf;lim letter Descr i Dt ive dew Jerminals mh9L7#8898108 nterim electrical parameters (see 4.2) 18283878 a,9, IO, 11 I 1,789 I 18789 roup D end-point electrical parameters (see 4.4) roup E

11、end-point electrical parameters (see 4.4) I I I I I I 1,7,9 1,7,9 1#789 1,7,9 1,7,9 8789 Input leakage current Static current roup A test requirements (see 4.4) IH i100 nA IDDSB 150 M I 7 1,28384#788, 9,10,11 I 182#384#7#8# 9,1D, 11 roup C end-point electrical parameters (see 4.4) U PDA applies to s

12、ubgroup 1 and 7. z/ PDA applies to subgroups 1,7 and deltas. ;2/ Delta limits as specified in Table IIB herein shall be required where specified and the delta values shall be completed with reference to the zero hour. TABLE IIB. Burn-in delta Darameters ( +2Sb 1. Parameter Delta limits Output low vo

13、ltage Output high voltage 1400 mV Input leakage current i100 nA 4.4.2.1 a. Additional criteria f or device class M. Steady-state life test conditions, method 1005 of MIL-STD-883: Test condition A, B, C or D. level control and shall be made available to the preparing or acquiring activity upon reques

14、t. circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005. The test circuit shall be maintained by the manufacturer der docunent revision The test b. TA = +125C, minimum. c. Test duration: 1,000 hours, exce

15、pt as permitted by method 1005 of MIL-STO-883. 5962-95824 REVISION LEVEL SHEET STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,- SUD-5962-95824 99

16、99996 0082553 791 SIZE A STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL . 5962-95824 SHEET 21 4.4.2.2 Additional cr iteria for device classes Q and V. The steady-state life test duration, test condition and test temperature, or approved alternatives

17、 shall be as specified in the device manufacturers PM plan in accordance with MIL-1-38535. manufacturers TRB, in accordance with MIL-1-38535, and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipa

18、tion, as applicable, in accordance with the intent specified in test method 1005. The test circuit shall be maintained under docunent revision level control by the device 4.4.3 Grow D mw ctiov. The group D inspection end-point electrical parameters shall be as specified in table Group E inspection i

19、s required only for parts intended to be -3rked as radiation IIA herein. 4.4.4 Wwr, E inswct im. hardness assured (see 3.5 herein). End-point electrical parameters shall be as specified in table IIA herein. RHA levels for device classes M, and V shall be as specified in UIL-1-38535. -. 4.4.4.1 Jota1

20、 d ose irradiati on testiu. Total dose irradiation testing shall be performed in accordance with UIL- STD-883 method 1019 and as specified herein. 4.4.4.1.1 Accelerated as ins test . Accelerated aging tests shall be performed on all devices requiring a RHA level greater than 5k radScSi). The post-an

21、neal end-point electrical parameter limits shall be as specified in table 1 herein and shall be the pre-irradiation end-point electrical parameter limit at 25.C t5.C. at initial qualification and after any design or process changes which may affect the RHA response of the device. Testing shall be pe

22、rformed 4.6.4.2 pose rate induced 1 atchur, test inq. Dose rate induced latchup testing shall be performed in accordance with test method 1020 of MIL-STD-883 and as specified herein (See 1.4). approved test structures at technology qualification and after any design or process changes which may effe

23、ct the RHA capabi 1 i ty of the process. shall be performed on a technology process on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as approved by the qualifying activity at initial qualification and after any design or process changes which may affect the upset or latchup cha

24、racteristics. The ion beam angle of incidence shall be between normal to the die surface and 60 to the normal, inclusive (i.e. O s angle s 60). Mo shadowing of the ion beam due to fixturing or package related effects is allowed. The fluence shall be 2 100 errors or 2 lo6 ions/cm2. The flux shall be

25、between lo2 and IO5 ions/cm2/s. The cross-section shall be verified to be flux independent by measuring the cross-section at two flux rates which differ by at least an order of magnitude. The particle range shall be 2 20 microns in silicon. The test temperature shall be +25.C and the maxim rated ope

26、rating temperature tlOC. Bias conditions shall be defined by the manufacturer for latchup measurements. Test four devices with zero failures. Tests shall be performed on devices, SEC, or 4.4.4.3 %-nale event Dh enornena (SEPL. SEP testing shall be required on class V devices (Sea 1.4). SEP testing l

27、he recoinnended test conditions for SEP are as follows: a. b. c. d. e. f. g. 4.5 on. Methods of inspection shall be specified as follows: 4.5.1 terminal. yoltaqe and c urrent. Unless otherwise specified, all voltages given are referenced to the microcircuit Vss Currents given are conventional curren

28、t and positive when flowing into the referenced terminal. 5. PACKAGING 5.1 Wkaaina reaui remem . The requirements for packaging shall be in accordance with MIL-STO-883 (see 3.1 herein) for device class M and MIL-1-38535 for device classes P and V. 6. NOTES 6.1 mend ed use. Microcircuits conforming t

29、o this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Beda ceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-prepared specification or drawing.

30、6.1.2 Substitutability. Device class Q devices will replace device class M devices. DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-6.2 Confiauration control of SMDlq. record for the individual docunents. Form 1692, Engineering

31、Change Proposal. All proposed changes to existing SHDls will be coordinated with the users of This coordination will be accomplished in accordance with MIL-STD-973 using OD 6.3 three-stated during Hold and Halt modes and during RESET. The most significant 8 bits of the memory address or the 8 bits o

32、f ADO-7 I/O Multiplexed address/data bus: Lower 8 bits of the memory address (or 1/0 address) appear on the bus during the first clock cycle (T state) of a machine cycle. then becomes the data bus during the second and third clock cycles. it ALE so, SI, and IdM - RD - UR READY O O I Address latch en

33、able: and enables the address to get latched into the on-chip latch of peripherals. falling edge of ALE is set to guarantee setup and hold times for the address information. information. ALE is never three-stated. It occurs during the first clock state of a machine cycle lhe The falling edge of ALE

34、can also be used to strobe the status Machine cycle status: - iO/n SI so Status O O 1 Memory write O 1 O Memory write 1 O 1 I/O write 1 1 O I/O read O 1 1 Opcode fetch 1 1 1 Opcode fetch 1 1 1 Interrupt acknowledge T O O Halt T X X Hold 1 X X Reset T = Three-state (high impedance) X = Unspecified S1

35、 can be used as an advanced R/W status. beginning of a machine cycle and remain stable throughout the cycle. edge of ALE may be used to latch the state of these lines. - - IO/M, SO, and SI becm valid at the The falling Read control: to be read and that the Data Bus is available for the data transfer

36、, three-stated during Hold and Halt modes and during RESET. Write control: A low level on UR indicates the data on the Data Bus is to be written into the selected memory or 1/0 location. edge of UR, three-stated during Hold and Halt modes and during RESET. A low level on RD indicates the selected me

37、mory or 1/0 device is - Data is set up at the trailing Ready: If READY is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive data. If READY is low, the cpu will wait an integral nunber of clock cycles for READY to go high before completing the r

38、ead or write cycle. hold times. READY must conform to specified setup and STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER 1 DAYTON, OHIO 45444 5962-95824 DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-59b2-9

39、5824 999999b 0082553 5b4 HOLD HLDA INTR INTA RST 5.5 RST 6.5 RST 7.5 TRAP - RESET IN RESET OUT x1 x2 CLK SI0 SOD VDD GND -ree I O I 1 I O I O O O Description - Continued. Hold: buses. The cpu, upon receiving the hold request, will relinquish the use of the bus as soon as the completion of the curren

40、t bus transfer. Internal processing can continue. The processor can regain the bus only a- -HOLD is rmved. Uhen the HOLD is acknowiedged, the Address, Data Bus, RD, UR, and idM lines ar three-stated. Hold acknowledge: it will relinquish the bus in the next clock cycle. HLDA goes low after the Hold r

41、equest is removed. low. interrupt request: during the next to the last clock cycle of an instruction and during Hold and Halt states. incrementing and an I NTA will be issued, During this cycle a RESTART or CALL instruction can be inserted to junp to the interrupt service routine. enabled and disabl

42、ed by software. interrupt is accepted. Interrupt acknowledge: Is used instead of (and has the same timing as) RD during the instruction cycle after an INTR is accepted. 82C59A interrupt chip or some other interrupt port. Restart interrupts: cause an internal RESTART to be automatically inserted. The

43、se interrupts have a higher priority than INTR. individually masked out using the SIM instruction. Trap: Trap interrupt is a normaskable RESTART interrupt. It is recognized at the same time as INTR or RST 5.5-7.5. Enable. Indicates that another master is requesting the use of the address and date In

44、dicates that the cpu has received the HOLD request and that The cpu takes the bus one half clock cycle after HLDA goes Is used as a general purpose interrupt. It is sampled only If it is actLthe Program Counter (PC) will be inhibited from The INTR is It is disable by Reset and immediately after an -

45、 It can be used to activate an These three inputs have the same timing as INTR except they In addition, they may be It is unaffected by any mask or Interrupt It has the highest priority of any interrupt. Reset in: HLDA flip-flops. during RESET and because of the asynchronous nature of RESET the proc

46、essors htemai ceejsters and flags may be altered by RESET with unpredictable results. R E SE 1 I N is a Schmitt-triggered input,aLh& g-cnnnection to an R-C network for power-on RESET delay. Upon power-*, RES ET I N must reniain low for at leas 10 %lock cycle“ after mini reached. For proper reset ope

47、ration after the power-up duration? RE E T I N should be kept low a minimn - clock periods. The CPU is held in the reset condition as long as RESET II is applied. Reset out: reset. nunber of clock periods. X1 and X2: clock generator. X, can also be an external clock input from a logic gate. The inpu

48、t frequency is divided by 2 to give the processorls internal operating frequency. Ctock: X1, X2 input period. Serial input data line: The data on this tine is loaded into accunulator bit 7 whenever a RIM instruction is executed. Sets the program counter to zero and resets the Interrupt Enable and Th

49、e data and address buses and the control lines are three-state Reset out indicates cpu is being reset. Can be used as a system The signal is synchronized to the processor clock and lasts an integral Are connected to a crystal, LC or RC network to drive the internal Clock output for use as a system clock. lhe period of CLK is twice the Serial output data line: instruction. The output SOD is set or reset as specified by the SIM Power: *5 V supply. Ground: Reference. I SIZE