DLA SMD-5962-94733-1995 MICROCIRCUIT MEMORY DIGITAL CMOS 12000 GATE CONFIGURABLE LOGIC ARRAY MONOLITHIC SILICON《数字的互补金属氧化物半导体1200配置逻辑排列硅单片电路线型微电路》.pdf

《DLA SMD-5962-94733-1995 MICROCIRCUIT MEMORY DIGITAL CMOS 12000 GATE CONFIGURABLE LOGIC ARRAY MONOLITHIC SILICON《数字的互补金属氧化物半导体1200配置逻辑排列硅单片电路线型微电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-94733-1995 MICROCIRCUIT MEMORY DIGITAL CMOS 12000 GATE CONFIGURABLE LOGIC ARRAY MONOLITHIC SILICON《数字的互补金属氧化物半导体1200配置逻辑排列硅单片电路线型微电路》.pdf（18页珍藏版）》请在麦多课文档分享上搜索。

1、- SMD-5962-94733 b 0071b01 251 m REVISIONS I I I SIZE A LTR 1 CAGE CODI., 5962-94733 67268 DESCRIPTION R-_ttt SHEET =-i- distrfbution is unlimited. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-1. SCOPE 1.1 Scope. This drawing forms a part of a one

2、 part - one part number documentation system (see 6.6 herein). Two product assurance classes consisting of mi Litary high rel.isbility (device classes Q and MI and space application (device class VI, and a choice of case outlines and lead finishes are available and are reflected in the Part or Ident

3、ifying Number (PIN). available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. Device class M microcircuits represent non-JAN class B microcircuits in accordance with When 1 1.2.1 of MIL-STD-883, “Provisions for the use of MIL-STD-883 in conjunction with compliant no

4、n-JAN devices“. 1.2 PIN. The PIN shall be as shown in the following exarnplr?: - 94733 - M X x I I I I I I I 5962 o1 I I I I I I II I Lead Case Devi ce t Devi ce Federa 1 RHA stock class designator tYFe cl3ss out 1 ine finish designator (1.2.1) (See 1.2.2) designator (See 1.2.4) (See 1.2.5) I (See 1

5、.2.3) f Drawing number 1.2.1 RHA designator. Device class M RHA marked devices shall meet the MIL-1-38535 appendix A specified RHA teveis and shall be marked with the appropriate RHA designator. MIL-1-38535 specified RNA levels ai?d shall be marked uith tle appropriate RHA designator. non-RHA device

6、. Cevice classes Q and V RHA marked devices shall meet the A dash (-1 indicates a 1.2.2 Device type(s). The device typeCs) shall identify the circuit function as fotlovs: Access time Device type Generic number - Circuit function - o1 81188-3 1Cc)S Logic cell configurable array 38.2 ns 1.2.3 Device c

7、lass desiqnator. The device class designsror shall be a single letter identifying the product assurance level as follows: Device class - Device requirements docurnewition M Vendor self-certification to the requirements for non-JAN class i3 microcircuits in eccordence with 1.2.1 of MIL-STO-883 Cert f

8、 Specifications and Standards specified in the solicitation, form a part sf this drawing to the extent specified lerein. SPECIFICATION MILITARY MIL-1-38535 - Integrated Circuits, Nanufacturing, General Specification for. STANDARDS MILITARY MIL-STD-883 - Test Methods and Proredures fcr Microelectroni

9、cs. NIL-STD-973 - Configuration Management. MIL-STD-1835 - Microcircuit Case Outlines. BULLETIN MILITARY MIL-BUL-103 - List of Standard Microcirctiit Drakings (SMDs). HANDBOOK MILITARY MIL-HDBK-780 - Standardized bliiitary Dravings. (Copies of the specifications, standards, bulletin, and hmdhook req

10、uired ts. Unless otherwise specified herein, the electrical performance characterirtics srd pcstirroaiatioii paranleter limits are ES specifipd in table I and shall apply over the full case operatin9 temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the s

11、ubgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Markinq. The part shall be marked uith the PIN 1i:;t-J ir; 1.2 herein. Marking for device class M shalt be in accordance uith MIL-STD-883 (see 3.1 herein). MIL-BUL-103. In additir?, the can:ifacturers

12、 PIN may also be marked as listed in Harking for device classes Q and V shall be ri accordance with MIL-1-38535. 3.5.1 Certification/compLiance mark. The cornplience mark for device class H shall be a “C“ as required in NIL-STD-883 (see 3.1 herein). The certification mark for device classes Q and V

13、shall be a “QML“ or “Pi as required in MIL-1-38535. . Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-, STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 SMD-5962-94733 b 0073605 T7 W SIZE 5962-94733 A REVISION LEVEL

14、SHEET 5 3.6 Certificate of compliance. For device class M, a certificate of compliance shall be required from a ianufacturer in order to be listed as an approved source of supply in HIL-BUL-103 (see 6.7.2 herein). :lasses Q and V, a certificate of compliance shall be required from a QML-38535 listed

15、 manufacturer in order to supply o the requirements of this drawing (see 6.7.1 herein). The certificate of compliance submltted to DESC-EC prior to .isting as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for levice class M, the requirements of MIL-

16、STD-883 (see 3.1 herein), or for device classes Q and V, the requirements of 1IL-1-38535 and the requirements herein. For device 3.7 Certificate of conformance. A certificate of conformance as required for device class M in MIL-STD-883 (see 5.1 herein) or for device classes Q and V in IIIL-1-3853s s

17、hall be provided with each Lot of microcircuits delivered to :his drawing. 3.8 Notification of chanqe for device class M. For device class M, notification to DESC-EC of change of product :see 6.2 herein) involving devices acquired to this drawing is required for any change as defined in MIL-STD-973.

18、 3.9 Verification and review for device class M. For device class M, DESC, DESCs agent, and the acquiring activity Offshore documentation -etain the option to review the manufacturers facility and applicable required documentation. ;hall be made available onshore at the option of the reviewer. 3.10

19、Microcircuit aroup assignment for device class M. Device class H devices covered by this drawing shall be in microcircuit group number 42 (see MIL-1-38535, appendix A). 4. QUALITY ASSURANCE PROVISIONS 4.1 Samplinq and inspection. For device class M, sampling and inspection procedures shall be in acc

20、ordance with For device classes Q and V, sampling and inspection procedures shall be in accordance !IL-STD-883 (see 3.1 herein). dith HIL-1-38535 and the device manufacturers QM plan. 4.2 Screeninq. For device cless M, screening shall be in accordance with method 5004 of MIL-STD-683, and shall be :o

21、nducted on all devices prior to quality conformance inspection. For device classes Q and V, screening shall be in iccordance with MIL-1-38535, and shall be conducted or. all devices prior to qualification and technology conformance inspection. 4.2.1 Additional criteria for device class H. a. Delete

22、the sequence specified as initial (pre-burn-in) electrical parameters through interim (post-burn-in) electrical parameters of method 5004 and substitute lines 1 through 6 of table IIA herein. For device class ri, the test circujt shall be maintained by the manufacturer under document revision level

23、control and shall be made available to the preparing or acquiring activity upon request. For device class M the test circuit shall specify the inputs, outpuKs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015. b. c. Interim and final electrica

24、t test parameters shall be as specified in table XIA herein 4.2.2 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature or approved alternatives shall be as specified in the device manufacturers QM plan in eccordance with MIL-1-38535. circu

25、it shall be maintained under docuvent revision level control of the device manufacturers Technology Review Board (TRB) in accordance with MIL-1-38535 and shall be made available to the acquiring-or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power

26、 dissipation, as applicable, in accordance with the intent specified in test method 1015. The burn-in test b. c. Interim and final electrical test parameters shall be as specified in table IIA herein. Additional screening for device class If beyond the requirerents of device class cl shall be as spe

27、cified ln appendix B of MIL-1-38535. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-94733 9999996 0071606 833 TABLE I. Electrical performance characteristics. I I I Test I Symbo 1 I I I I I I I i ?OH High level output voltage Low level outp

28、ut !VOL VCC standby supply IICCO voltage current Input leakage current I Output leakage current I Input capacitance I ?IN 1 Output capacitance I ?OUT I Funct iona 1 test I I Register to register via ItDRR interconnects and 4 local I interconnects Max nstatus pin low time 4 logic elements, 3 row - I

29、ItSTAT I 8 Conditions Group A -55?C d TC I +12SnC unless othervise specified I vcc = 4.5 v VIL = 0.8 V I 1,2,3 IO, = -4.0 mA VIH = 2.0 V I Vcc f 5.5 V , VIL I 0.8 V I IoL - 8.0 mA, VIH - 2.0 V I I subgroups 4.5 v 5 vcc 9 5.5 v I I I I 1,2,3 V1 = Vcc or GND i 1,2,3 I I VIN = O V and 5.5 V l 1,2,3 vcc

30、 = 5.5 v I I VIN = O V and 5.5 V I 1,2,3 vcc = 5.5 v I I I See 4.4.le 14 I See 6.4.le 14 See 5.4.1 I7,8A, 85 I I I I I 1 9,10,11 i I 9,10,11 -I I I )evicej Limits i Unit type I I I I Min I Max I I I I All i 2.4 i i V I I I I I I I I I 1 I I V I 0.45 I All I AL1 I i 10 I mA I I I I l I I I I 1 I I I

31、I I I I I All I I 75 I AL I l I All I I 75 I I All I I I I I I I 01 I 1 I 1 I I I I I I 01 I I 100 I I I I All I -10 I +lo I jlA All I -40 I + 2 E3 E4 E7 E8 E9 I 10 Devi ce type Terminal number AI A2 A3 A4 A5 A6 A7 A8 A9 Al O Al I AI 2 Al 3 Al 4 Al 5 Al 6 Al 7 BI 02 83 84 85 86 87 I38 89 BI O BI 1 B

32、I 2 BI 3 81 4 81 5 816 BI 7 CI c2 c3 c4 C = NO CONN All Terminal syrnbo I GND I/O I /o I /o I /o I /o I/O I/O I /o I/O I /o I /o I/O I /o I /o I/O I /o I /o Il0 I /o I /o I /o I /o I /o I /o 1/0 Il0 I /o 1 /o I/O I /o I /o I/O I /o INPUT I /o I /o DCLK T I/O I/O f /o I /o I /o I /o I /o I /o Il0 NSP

33、 1 /o I /O INPUT I /o I/3 I /o I/O I /cl GP!D I/O I /o I /o I /o I /3 I/O I /u I /o I /o I/O Il0 I /o I /o I /o VCCJFIT GF:D VCCIO G!D VCCIO -u_ FIGURE 1. Terminil sornections. Devi ce Terminal Termi na 1 number sysbo 1 El 1 El 4 El 5 El 6 E17 FI F2 F3 F4 F5 FI3 FI4 FI 5 FI6 FI7 G1 G2 C3 G4 65 GI3 G

34、I% GI 5 GI6 GI7 HI t13 H4 H5 til 3 H14 ti15 !I5 HI 7 JI J2 n2 GND VCCINT I/O I /o I /o I /o I /o I /o I /o VCCIO VCCIO I /O I /o I /o I/O I/O I/O CONF-DONE GND GND GND GEID MSELO I/O I /o I /o I/O I /o VCCINT VCCI9 VCCIO VCCIN T I /o I /o I /o I /o I /o J3 I I/O 5962-94733 REVISION LEVEL SHEET STAND

35、ARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-Device type STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER Termi na 1 number 5962-947

36、33 J4 J5 JI3 JI4 JI5 JI6 JI7 KI Kz K3 K4 u5 KI 3 KI 4 KI 5 KI 6 KI 7 LI u L3 L4 L5 LI 3 LI 4 LI 5 LI 6 LI7 MI M2 M3 M4 H5 HI 3 MI 4 MI 5 MI 6 MI 7 NI N2 : NO CONNI SMD-57b2-74733 Case outline X - Continued. ALL Termi na 1 symbol I/O GND GND I /o I /o I /o I /o I/O I/O I /o GND VCCIO VCCIO GND I /o I

37、/O I /o I/O I /o NSTATUS VCCINT GND GND VCCINT MSELI I /o I /o I /o I /o I /o i/O VCCIO VCCIO I /o I/O I /o I/O I /o 1 /o Devi ce type Termi na I number N3 N4 N7 N8 N9 NI0 NI 1 NI 4 NI 5 NI 6 NI 7 PI P2 P3 P4 P5 P6 P7 P8 P9 PI o PI 1 PI 2 PI 3 PI 4 PI 5 PI 6 PI 7 RI R2 R3 R4 R5 R6 R7 R8 R9 RI O RI 1

38、 RI 2 ALL Termi na 1 symbol I /o GND GN D VCCIC GN D VCCIO GtiD GND I /o I/O I /o I /o I io I/O I /o I /o I10 I /o I /o I /o If0 1 /3 VCCLNT : IC; I/O I /o I /o I/O INPUT I /O I /O NCOYI IS I/O I /o I /o I /o I /o I /o I/O I/D Devi ce type Te rm i na 1 number RI 3 RI 4 RI 5 RI6 RI 7 TI T2 T3 T4 T5 T

39、6 T7 T8 T9 TI0 TI 1 TI 2 TI 3 TI4 TI 5 TI 6 TI 7 U1 u2 L3 w u5 U6 u7 U8 ti9 u10 111 1 u1 2 u1 3 u14 111 5 U16 CI7 FIGURE I. Termiris; ccnnoctions - Continued. ALL Term i na 1 symbol I /o VCCINT I /o I/O INPUT I /o 1 /o I /o 110 I/O I /o If0 I /o I /o I/O U0 I /o J. /O I /o Il0 I /o I/O VCCINT I /o I

40、 /o I /o I /o I/O If0 I /O I /o I /o I /o I /o I /o Il0 I /o I /o I /o DAYTON, OHIO 45444 I REVISION LEVEL SHEET I 11 DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-94733 9999996 0071612 037 = Input pins Dedicated inpu

41、t X Output pins I/O 2 FIGURE 2. Truth table (unconfisured). REVISION LEVEL STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 I I 5962-947: SHEET 12 DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,

42、-SND-59b2-94733 W b 0071b13 T73 4.3 Qualification inspection. 4.3 Qualification insDection for device classes Q and V. Qualification inspection for device classes Q and V shall Inspections to be performed shall be those specified in MIL-1-38535 and herein for be in accordance with MIL-1-38535. group

43、s A, 6, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4 Conformance inspection. Quality conformance inspection for device class M shall be in accordance with MIL-STD-883 (see 3.1 herein) and as specified herein. Inspections to be performed for device class M shall be those specified in method

44、 5005 of MIL-STD-833 and herein for groups A, B, C, D, and E inspections (see 4.4.1 thrwgh 4.4.4). Technology conformance inspection for classes Q and V shall be in accordance with MIL-1-38535 including groups A, B, C, D, and E inspections and as specified herein except where option 2 of MIL-1-38535

45、 permits alternate in-line control test i ng . 4.4.1 a. b. C. d. e. Group A inspection. Tests shall be as specified in table ZIA herein. Subgroups 5 and 6 of table I of method 5005 of MIL-STD-883 shall be omitted. For device class M subgroups 7, 8 and 8B tests shrll consist of verifying functionalit

46、y of the device. request. of the device; these tests shall have been fault graded in accordance with MIL-STO-883, test method 5012 (see 1.5 herein). These tests form a part of the vendors test tape and shall be maintained and available upon For device classes P and V subgroups 7, 8r wd 8B shall incl

47、ude verifying the functionality O/V (latch-up) tests shalt be measured only for initial quali+ication and after any design or process changes which may affect the performance of the device. shall be maintained under document revision level control by the manufacturer and shall be made available to t

48、he preparing activity or acquiring activity upon request. For device classes P and V, the procedures and circuits shall be uider the control of the device manufacturers technical review board (TRB) in accordance with MIL-1-38535 and shat! be made available to the preparing activity or acquiring acti

49、vity upon request. Latch-up test shall be considered destructive. be used for reference. For device class M procedures and circuits Testing shalt be on al! pi%, on 5 devices with zero failures. Infarmation contained in JEDEC standard number 17 may Subgroup 4 (ClN and COUT measuremepts) shall be Reasured only for initial qualification and after any process or design changes which may affect input or output c