DLA SMD-5962-91725 REV A-2008 MICROCIRCUIT DIGITAL BIPOLAR CMOS SCAN TEST DEVICE WITH OCTAL D-TYPE LATCH THREE-STATE OUTPUTS MONOLITHIC SILICON《单片硅三相输出扫描测试装置带8D型锁存器双极CMOS数字微电路》.pdf

《DLA SMD-5962-91725 REV A-2008 MICROCIRCUIT DIGITAL BIPOLAR CMOS SCAN TEST DEVICE WITH OCTAL D-TYPE LATCH THREE-STATE OUTPUTS MONOLITHIC SILICON《单片硅三相输出扫描测试装置带8D型锁存器双极CMOS数字微电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-91725 REV A-2008 MICROCIRCUIT DIGITAL BIPOLAR CMOS SCAN TEST DEVICE WITH OCTAL D-TYPE LATCH THREE-STATE OUTPUTS MONOLITHIC SILICON《单片硅三相输出扫描测试装置带8D型锁存器双极CMOS数字微电路》.pdf（22页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update boilerplate to current MIL-PRF-38535 requirements. - MAA 08-08-11 Thomas M. Hess REV SHEET REV SHEET REV A A A A A A A SHEET 15 16 17 18 19 20 21 REV A A A A A A A A A A A A A A REV STATUS OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 P

2、MIC N/A PREPARED BY Thanh V. Nguyen CHECKED BY Thanh V. Nguyen DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218 - 3990 http:/www.dscc.dla.mil APPROVED BY Monica L. Poelking DRAWING APPROVAL DATE 94-01-06 MICROCIRCUIT, DIGITAL, BIPOLAR CMOS, SCAN TEST DEVICE WITH OCTAL D-TYPE LATCH, THREE-STATE OU

3、TPUTS, MONOLITHIC SILICON SIZE A CAGE CODE 67268 5962-91725 STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A REVISION LEVEL A SHEET 1 OF 21 DSCC FORM 2233 APR 97 5962-E450-08 Provided by IHSNot for ResaleNo reproduc

4、tion or networking permitted without license from IHS-,-,-SIZE A 5962-91725 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218 - 3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting

5、 of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.

6、2 PIN. The PIN is as shown in the following example: 5962 - 91725 01 M L A Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q

7、and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device

8、. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54BCT8373A Scan test device with octal D-type latch, three-state outputs. 1.2.3 Device class designator. The device class designator is a single letter identifying the

9、product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. Q or V Certification and qualification to MIL-PRF-38535 1.2.

10、4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style L GDIP3-T24 or CDIP4-T24 24 Dual-in-line 3 CQCC1-N28 28 Square leadless chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38

11、535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-91725 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218 - 3990 REVISION LEVEL

12、A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage range (except Test Mode Select (TMS) (VIN). -0.5 V dc to +7.0 V dc 4/ DC input voltage range (Test Mode Select) (VIN). -0.5 V dc to +12.0 V dc 4/ DC output voltag

13、e range applied to any output in the disabled or power-off state (VOUT) -0.5 V dc to +5.5 V dc DC output voltage range applied to any output in the high state (VOUT). -0.5 V dc to VCCDC input clamp current (IIK) . -30 mA DC output current into any output in the low state (IOL) (per output): Test Dat

14、a Output (TDO). +40 mA Any Q. +96 mA Maximum power dissipation (PD) . 497 mW 5/ Storage temperature range (TSTG) . -65C to +150C Lead temperature (soldering, 10 seconds). +300C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) +175C 1.4 Recommended operating cond

15、itions. 2/ 3/ Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Maximum low level input voltage (VIL) +0.8 V Minimum high level input voltage (VIH). +2.0 V Double high level input voltage at TMS (VIHH) +10.0 V dc min. to +12.0 V dc max. Maximum input clamp current (IIK) . -18 mA Maximum high level o

16、utput current (IOH): Test Data Output (TDO). -3 mA Any Q. -12 mA Minimum setup time (tS): Data before LE 3.0 ns Any D before test clock (TCK) . 6.0 ns LE or OE before TCK 6.0 ns Test data input (TDI) before TCK 6.0 ns TMS before TCK . 12.0 ns Minimum hold time (th): Data after LE . 2.0 ns Any D afte

17、r test clock (TCK) 4.5 ns LE or OE after TCK . 4.5 ns Test data input (TDI) after TCK . 4.5 ns TMS after TCK 0.0 ns Minimum pulse width (tW): LE high. 5 ns Test clock (TCK) high or low 25 ns TMS double high 50 ns 6/ Minimum delay time (td), power-up to TCK 100 ns 6/ Maximum TCK frequency (fCLK) . 20

18、 MHz Case operating temperature range (TC). -55C to +125C 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise noted, all voltages are referenced to GND. 3/

19、 The limits of the parameters specified herein shall apply over the full specified VCCrange and case temperature range of -55C to +125C. 4/ The input negative voltage ratings may be exceeded provided that the input clamp current rating is observed. 5/ Power dissipation values are derived using the f

20、ormula PD= VCC ICC+ n (VOLx IOL), where VCC and IOLare specified in 1.4 above, ICCand VOL are as specified in table I herein, and n represents the total number of outputs. 6/ This parameter is not production tested. Provided by IHSNot for ResaleNo reproduction or networking permitted without license

21、 from IHS-,-,-SIZE A 5962-91725 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218 - 3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbook

22、s form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DE

23、FENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are

24、 available online at http:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document (s) form a part of this document to the extent specified herein. Unless

25、otherwise specified, the issues of the documents which are DOD adopted, and those listed in the issues of the DODISS cited for solicitation. Unless otherwise specified, the issues of documents not listed in the DODISS are the issues of the documents cited for the solicitation. INSTITUTE OF ELECTRICA

26、L AND ELECTRONICS ENGINEERS (IEEE) IEEE Standard 1149.1 IEEE Standard Test Access Port and Boundary Scan Architecture. (Applications for copies should be addressed to the Institute of Electrical and Electronics Engineers, 445 Hoes Lane, Piscataway, NJ 08854-4150) (Non-Government standards and other

27、publications are normally available from the organizations that prepare or distribute the documents. These documents may also be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references

28、 cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accord

29、ance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MI

30、L-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein

31、 for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-91725 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218

32、- 3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Block or Logic diagram. The block or logic diagram shall be as specified on figure

33、 3. 3.2.5 Test access port controller and scan test registers. The test access port (TAP) controller and scan test register shall be as specified on figure 4. 3.2.6 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 5. 3.3 Electrical perfor

34、mance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and post-irradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirement

35、s. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking

36、of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535.

37、Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-

38、38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be require

39、d from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q

40、 and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix

41、A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawi

42、ng. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.

43、10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 127 (see MIL-PRF-38535, appendix A). 3.11 IEEE 1149.1 compliance. This device shall be compliant with IEEE 1149.1 Provided by IHSNot for ResaleNo reproduction or

44、networking permitted without license from IHS-,-,-SIZE A 5962-91725 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218 - 3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Limits 3/ Test and MIL-STD-883 test method 1/ S

45、ymbol Test conditions 2/ -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified VCCGroup A subgroups Min Max Unit 4.5 V 1, 2, 3 2.5 IOH= -1.0 mA 4.75 V 1, 2, 3 2.7 High level output Voltage, TDO 3006 VOH1IOH= -3.0 mA 4.5 V 1, 2, 3 2.4 4.5 V 1, 2, 3 2.4 IOH= -3.0 mA 4.75 V 1, 2, 3 2.7 High level

46、output Voltage, any Q 3006 VOH2For all inputs affecting output under test VIN= 2.0 V or 0.8 V IOH= -12.0 mA 4.5 V 1, 2, 3 2.0 V Low level output Voltage, TDO 3007 VOL1IOL= +20 mA 4.5 V 1, 2, 3 0.5 Low level output Voltage, any Q 3007 VOL2For all inputs affecting output under test VIN= 2.0 V or 0.8 V

47、 IOL= +48 mA 4.5 V 1, 2, 3 0.55 V Negative input clamp voltage 3022 VIC-For input under test, IIN= -18 mA 4.5 V 1, 2, 3 -1.2 V IIH1For input under test, VIN= 5.5 V 5.5 V 1, 2, 3 +100 Input current high 3010 IIH2For input under test, VIN= 2.7 V 5.5 V 1, 2, 3 -1.0 -100 A Double input current high 3010

48、 IHHVIN= 10.0 V Test mode select (TMS) 5.5 V 1, 2, 3 +1.0 mA Input current low 3009 IILFor input under test, VIN= 0.5 V 5.5 V 1, 2, 3 -200 A TDO 1, 2, 3 -1.0 -100 Off-state output leakage current high 3021 IOZHFor control input affecting output under test, VIN= 2.0 V VOUT= 2.7 V Any Q 5.5 V 1, 2, 3 +50 A TDO 1, 2, 3 -200 Off-state output leakage current low 3020 IOZLFor control input affecting output under test, VIN= 2.0 V VOUT= 0.5 V Any Q 5.5 V 1, 2, 3 -50 A Output short circuit current 3011 IOS 4/ VOUT= 0.0 V 5.5 V 1,