DLA SMD-5962-89951 REV A-2011 MICROCIRCUITS MEMORY DIGITAL NMOS 512 X 8 BIT NONVOLATILE STATIC RAM MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Updated body of drawing to reflect current requirements. - glg. 11-07-06 Charles F. Saffle The original first page of this drawing has been replaced. REV SHET REV SHET REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 1

2、0 11 12 13 14 PMIC N/A PREPARED BY Charles Reusing DLA LAND AND MARITIME STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles Reusing COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUITS, MEMORY, DIGITA

3、L, NMOS, 512 X 8 BIT NONVOLATILE STATIC RAM, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 90-12-21 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-89951 SHEET 1 OF 14 DSCC FORM 2233 APR 97 5962-E411-11 .Provided by IHSNot for ResaleNo reproduction or netwo

4、rking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89951 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B

5、microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89951 01 V A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) ide

6、ntify the circuit function as follows: Endurance Device type 01 02 03 Generic number 2212 2212 2212 Circuit function 256 x 4 bit, nonvolatile static RAM 256 x 4 bit, nonvolatile static RAM 256 x 4 bit, nonvolatile static RAM Access time 300 ns 300 ns 300 ns Store cycles 10,000 50,000 100,000 Data ch

7、anges per bit 1,000 5,000 10,000 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style V GDIP1-T18 and CDIP2-T18 18 dual-in-line package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-

8、38535, appendix A. 1.3 Absolute maximum ratings. Temperature under bias- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -65C to +135C Storage temperature (TSTG) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -65C to +150C Voltage on any pin with respect to ground -

9、- - - - - - - - - - - - - - - - - - - - -1.0 V to +7.0 V dc DC output current - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 5.0 mA Lead temperature (soldering, 10 seconds) (TSOL)- - - - - - - - - - - - - - - - 300C Power dissipation (PD) - - - - - - - - - - - - - - - -

10、- - - - - - - - - - - - - - - - - - 0.50 W Thermal resistance, junction-to-case (JC)- - - - - - - - - - - - - - - - - - - - - See MIL-STD-1835 Junction temperature (TJ) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 150C 1.4 Recommended operating conditions. Supply voltage (VCC) - -

11、 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 4.5 V dc to 5.5 V dc Minimum high level input voltage (VIH)- - - - - - - - - - - - - - - - - - - - - - - - +2.0 V dc Maximum high level input voltage (VIH) - - - - - - - - - - - - - - - - - - - - - - - +VCC+ 1.0 V dc Minimum low le

12、vel input voltage (VIL) - - - - - - - - - - - - - - - - - - - - - - - - -1.0 V dc Maximum low level input voltage (VIL) - - - - - - - - - - - - - - - - - - - - - - - - +0.8 V dc Case operating temperature range (TC) - - - - - - - - - - - - - - - - - - - - - - - -55C to +125C Provided by IHSNot for R

13、esaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89951 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The

14、 following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufactu

15、ring, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Micr

16、ocircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this d

17、rawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordan

18、ce with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-3853

19、5 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall

20、 not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The desi

21、gn, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The tru

22、th table shall be as specified on figure 2. 3.2.4 Block diagram. The block diagram shall be as specified on figure 3. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full ca

23、se operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall

24、 be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/complia

25、nce mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. Provided

26、by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89951 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditi

27、ons -55C TC +125C VSS= 0 V, 4.5 V VCC 5.5 V (Unless otherwise specified) Device type Group A subgroups Limits Unit Min Max Input low voltage VILAll 1, 2, 3 -1.0 0.8 V Input high voltage VIHAll 1, 2, 3 2.0 VCC+ 1.0 V Output low voltage VOLVIL= 0.8 V, VIH= 2.0 V, IOL= 4.2 mA All 1, 2, 3 0.4 V Output h

28、igh voltage VOHVIL= 0.8 V, VIH= 2.0 V, IOH= -2 mA All 1, 2, 3 2.4 V Input load current ILIVIN= GND to VCC All 1, 2, 3 10 A Output leakage current ILOVOUT= GND to VCCAll 1, 2, 3 10 A Power supply current ICCAll inputs = VCC,II/0= 0 mA All 1, 2, 3 70 mA Input capacitance CINVIN= 0 V, TA= 25C, Frequenc

29、y = 1.0 MHz, VCC= 5 V, See 4.3.1c 1/ All 4 6 pF Output capacitance CI/OVI/0= 0 V, TA= 25C, Frequency = 1.0 MHz, VCC= 5 V, See 4.3.1c 1/ All 4 8 pF Read cycle time tRCSee figure 4 2/ All 9, 10, 11 300 Access time tASee figure 4 2/ All 9, 10, 11 300 ns Chip select to output valid tCOSee figure 4 2/ Al

30、l 9, 10, 11 200 ns Output hold from address change tOHSee figure 4 2/ All 9, 10, 11 50 ns Chip select to output to low Z tLZSee figure 4 2/ All 9,10,11 10 ns Chip deselect to output in high Z tHZSee figure 4 2/ All 9,10,11 10 100 ns Write cycle time tWCSee figure 5 2/ All 9,10,11 300 ns Chip select

31、to end of write tCWSee figure 5 2/ All 9,10,11 150 ns Address setup time tASSee figure 5 2/ All 9,10,11 50 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89951 DLA LAND AND

32、MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions-55C TC +125C VSS= 0 V, 4.5 V VCC 5.5 V (Unless otherwise specified) Device type Group A subgroups Limits Unit Min Max Write pulse widt

33、h tWPSee figure 5 2/ All 9,10,11 150 ns Write recovery time tWRSee figure 5 2/ All 9,10,11 25 ns Data valid to end of write tDWSee figure 5 2/ All 9,10,11 100 ns Data hold time tDHSee figure 5 2/ All 9,10,11 20 ns Write enable to output in high Z tWZSee figure 5 2/ All 9,10,11 10 100 ns Output activ

34、e from end of write cycle tOWSee figure 5 2/ All 9,10,11 10 ns Store cycle time tSTCSee figure 6 2/ All 9,10,11 10 ns Store pulse width tSTPSee figure 6 2/ All 9,10,11 100 ns Store to output in high Z tSTZSee figure 6 2/ All 9,10,11 500 ns Output active from end of store tOSTSee figure 6 2/ All 9,10

35、,11 10 ns Array recall cycle time tRCCSee figure 6 2/ All 9,10,11 1200 ns Recall pulse width tRCP 3/See figure 6 2/ All 9, 10, 11 450 ns Recall output in high Z tRCZSee figure 6 2/ All 9, 10, 11 150 ns Output active from end of recall tORCSee figure 6 2/ All 9, 10, 11 10 ns Recalled data access time

36、 from end of recall tARCSee figure 6 2/ All 9, 10, 11 750 ns 1/ Tested initially and after any design or process changes which may affect this parameter, and is guaranteed to the limits specified in table I. 2/ AC test conditions: Input high level VIH= 3.0 V. Input low level VIL= 0.0 V. Input rise/f

37、ail times tR= 10 ns. Output voltage high VIH 1.5 V. Output voltage low VIL 1.5 V. Output load CL= 100 pF. Input and output timing levels = 1.5 V. 3/ Array recall rise time must be less than 1 s. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDAR

38、D MICROCIRCUIT DRAWING SIZE A 5962-89951 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-1

39、03 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A cer

40、tificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime-VA shall be required for any change that affects this drawing. 3.9 Verification and

41、 review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 4. VERIFICATION 4.1 Sampling an

42、d inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria sh

43、all apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition C or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing activity upon request. The test circuit shall specify the inputs, outputs, bi

44、ases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional

45、 at the discretion of the manufacturer. 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-883 including groups A, B, C, and D inspections. The following additional criteria shall apply. 4.3.1 Group A inspection. a. Tests shall be as

46、 specified in table II herein. b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. c. Subgroup 4 (CINand CI/Omeasurements) shall be measured only for the initial test and after process or design changes which may affect capacitance. d. Subgroups 7 and 8 shall include verifi

47、cation of the truth table. 4.3.2 Groups C and D inspections. a. End-point electrical parameters shall be as specified in table II herein. b. Steady-state life test conditions, method 1005 of MIL-STD-883. (1) Test condition C or D. The test circuit shall be maintained by the manufacturer under docume

48、nt revision level control and shall be made available to the preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. (2) TA= +125C, minimum. (3) Test dura

49、tion: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89951 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 Devi