DLA SMD-5962-88532 REV C-2003 MICROCIRCUITS LINEAR 9 BIT A D CONVERTER MONOLITHIC SILICON《硅单片9位A D变流器线性微电路》.pdf

《DLA SMD-5962-88532 REV C-2003 MICROCIRCUITS LINEAR 9 BIT A D CONVERTER MONOLITHIC SILICON《硅单片9位A D变流器线性微电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-88532 REV C-2003 MICROCIRCUITS LINEAR 9 BIT A D CONVERTER MONOLITHIC SILICON《硅单片9位A D变流器线性微电路》.pdf（15页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R039-92. sbr 91-11-13 M. A. Frye B Drawing updated to reflect current requirements. Editorial changes throughout. drw 01-05-21 Raymond Monnin C Add case outline T. - drw 03-01-21 Raymond Monnin THE ORIGINAL FIR

2、ST PAGE OF THIS DRAWING HAS BEEN REPLACED REV SHET REV SHET REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Joseph A. Kerby DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY David H. Johnson COLUMBUS, OHIO 43216 h

3、ttp:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUITS, LINEAR, 9 BIT A/D CONVERTER, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 88-05-11 AMSC N/A REVISION LEVEL C SIZE A CAGE CODE 67268 5962-88532 S

4、HEET 1 OF 14 DSCC FORM 2233 APR 97 5962-E189-03 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88532 DEFENSE SUPPLY CENTER COL

5、UMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complet

6、e PIN is as shown in the following example: 5962-88532 01 X A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type. The device type identify the circuit function as follows: Device type Generic number Circuit function 01 TDC1049 9-Bit A/D converte

7、r 1.2.2 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style T See figure 1 68 quad flatpack U CQCC2-J68 68 J-lead chip carrier X CDIP1-T64 64 dual-in-lineY See figure 1 64 dual-in-line Z CQCC1-N68 68 square

8、leadless chip carried 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. VEEDto DGND+0.5 V dc to -7.0 V dc VEEAto AGND+0.5 V dc to -7.0 V dc VEEAto VEED+0.5 V dc to -0.5 V dc AGNDto DGND. +1.0 V dc to -1.0 V dc VIN, VRT, or VRBto AGND. +0.5

9、 V dc to VEECONV or CONV to DGND. +0.5 V dc to VEEVRTto VRB+2.5 V dc to -2.5 V dc Output short circuit duration . Indefinite Storage temperature range. -65C to +150C Lead temperature (soldering, 10 seconds). +300C Power dissipation, worst case (PD). 6.07 W Thermal resistance, junction-to-case (JC):

10、Cases U, X and Z See MIL-STD-1835 Case Y. 12C/W Case T . 20C/W Junction temperature (TJ). +175C Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88532 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 R

11、EVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Digital supply voltage to DGND(VEED) -4.9 V dc to -5.5 V dc Analog supply voltage to AGND(VEEA). -4.9 V dc to -5.5 V dc Analog ground voltage to AGND(VAGND) -0.1 V dc to +0.1 V dc Supply voltage differential (VEEA- V

12、EED) . -0.1 V dc to +0.1 V dc CONV pulse width, low (tPWL). 12 ns minimum CONV pulse width, high (tPWH). 15 ns minimum CONV input voltage, common mode (VICM) . -0.5 V dc to -2.5 V dc CONV input voltage, differential (VIDF) +0.3 V dc to +1.2 V dc Most positive reference input (VRT) 1/ -0.1 V dc to +0

13、.1 V dc Most negative reference input (VRB) 1/ -1.9 V dc to -2.1 V dc Voltage reference differential (VRT- VRB) 1.8 V dc to 2.1 V dc Input voltage (VIN) VRBto VRTOperating case temperature range (TC) . -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The

14、following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, ci

15、ted in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. HANDBOOK

16、S DEPARTMENT OF DEFENSE MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D

17、, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption h

18、as been obtained. 1/ VRTmust be more positive than VRB, and VRT VRBmust be within the specified range. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88532 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216

19、-5000 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified

20、Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38

21、535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in ac

22、cordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in

23、 accordance with 1.2.2 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table. The truth table shall be as specified on figure 3. 3.2.4 Block diagram. The logic diagram shall be as specified on figure 4. 3.3 Electrical performan

24、ce characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table I

25、I. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked as listed in MIL-HDBK-103 (see 6.6 herein)

26、. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to

27、MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to

28、 be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein

29、. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required in accordance with MIL-PRF-38535, append

30、ix A. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reprodu

31、ction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88532 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TC +125C

32、unless otherwise specified Group A subgroups Device type Limits Unit Min MaxSupply current IEEVEED= VEEA= -5.5 V 1, 2, 3 All -1090 mA Reference current IREFVRT= 0.0 V, VRB= -2.0 V, VEEA, VEED= -5.5 V 1, 2, 3 All 36 mA Total reference resistance 2/ RREFVRT= 0.0 V, VRB= -2.0 V 1, 2, 3 All 56 200 Input

33、 equivalent resistance 2/ RINVRT= 0.0 V, VRB= -2.0 V 1, 2, 3 All 16 k Input capacitance 2/ CINVRT= 0.0 V, VRB= -2.0 V 4, 5, 6 160 pF Input constant bias current ICBVIN= 0.0 V, VEEA= VEED= 5.5 V 1, 2, 3 All 750 A Digital input current (CONV, CONV) IIVI= 0.7 V, VEEA= VEED= -5.5 V 1, 2, 3 All 180 A Out

34、put low voltage VOLVEEA, VEED= -4.9 V 3/ 1, 2, 3 All -1.5 V Output high voltage VOHVEEA, VEED= -5.5 V 3/ 1, 2, 3 All -1.1 V Digital input capacitance 2/ CITA= 25C, f = 1.0 MHz 4 All 20 pF Maximum conversion rate 2/ FS VEEA, VEED= -4.9 V 4, 5, 6 All 30 MSPS 4/ Functional tests VEEA, VEED= -5.2 V, FS=

35、 1.0 MSPS (check output coding), see 4.3.1b 7, 8 All Sampling time offset 2/ tSTOSee figure 5 9, 10, 11 All -2.0 6.0 ns Digital output delay tDVEEA, VEED= -4.9 V 3/ See figure 5 9, 10, 11 All 31 ns Digital output hold time tHOSee figure 5 9, 10, 11 All 3.0 ns See footnotes at end of table. Provided

36、by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88532 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued

37、. Test Symbol Conditions 1/ -55C TC +125C unless otherwise specified Group A subgroups Device type Limits Unit Min MaxLinearity error integral ELIVRT= 0.0 V, VRB= -2.0 V, FS= 100 kHz 4, 5, 6 All 0.2 % Linearity error, differential ELDVRT= 0.0 V, VRB= -2.0 V, FS= 100 kHz 4, 5, 6 All 0.1 % Nominal cod

38、e size Q VRT= 0.0 V, VRB= -2.0 V, FS= 100 kHz 4, 5, 6 All 15 185 % Offset error, top 2/ EOTSVIN= VRT, RTSconnected 1, 2, 3 All 4.0 mV EOTVIN= VRT1, 2, 3 All 0 +30 Offset error, bottom 2/ EOBSVIN= VRB, RBSconnected 1, 2, 3 All 4.0 mV EOBVIN= VRB1, 2, 3 All 0 -30 Temperature coefficient of offset erro

39、r 2/ EOT VIN= VRB1, 2, 3 All 20 V/C Bandwidth, full power input 2/ BW 4, 5, 6 All 15 MHz Signal-to-noise ratio SNR Peak signal/ 1.25 MHz input 4, 5, 6 All 57 dB (30 MSPS conversion RMS noise 5.0 MHz input 4, 5, 6 All 53 rate, 10 MHz bandwidth) 2/ RMS signal/ 1.25 MHz input 4, 5, 6 All 48 RMS noise 5

40、.0 MHz input 4, 5, 6 All 44 Differential phase error 2/ DP FS= 4 X NTSC subcarrier 4, 5, 6 All 0.5 degrees Differential gain error 2/ DG FS= 4 X NTSC subcarrier 4, 5, 6 All 1.5 % 1/ Unless otherwise specified, characteristics apply over the recommended operating conditions specified in 1.4 herein. 2

41、/ Guaranteed if not tested. 3/ Test load = 500 ohms to 2.0 V, and 20 pF to ground. 4/ Mega samples per second. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88532 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OH

42、IO 43216-5000 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 Inches Millimeters Symbol Min Max Min Max A 0.070 0.100 1.778 2.540 A1 0.075 0.115 1.905 2.921 b 0.009 0.015 0.229 0.381 c 0.004 0.008 0.102 0.203 D/E 0.942 0.968 23.93 24.59 e 0.045 0.055 1.143 1.397 L 0.360 0.410 9.144 10.41 NOTES: 1. In

43、 case of conflict between the English and metric dimensions, the English dimensions control. FIGURE 1. Case outline T. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88532 DEFENSE SUPPLY CENTER COLUMBUS COLU

44、MBUS, OHIO 43216-5000 REVISION LEVEL C SHEET 8 DSCC FORM 2234 APR 97 Inches Millimeters Inches Millimeters Symbol Min Max Min Max Notes Symbol Min Max Min Max Notes A .110 .225 2.79 5.72 3 E3 .025 - - .053 - - A1 .050 .105 1.27 2.67 3 e .100 BSC 2.54 BSC b .014 .023 0.35 0.58 eA .900 BSC 22.86 BSC 5

45、 b1 .030 .070 0.78 1.78 eB - - 1.050 - - 26.67 6 c .007 .015 0.18 0.38 L .125 .200 3.17 5.08 3 D 3.170 3.240 80.52 82.30 4 Q1 .026 .035 0.66 0.89 E .880 .940 22.35 23.88 5 Q2 .005 - - 0.13 - - 9 E1 .790 .810 20.07 20.57 4 S .030 .100 0.76 2.54 E2 .640 .680 16.26 17.27 S1 .005 .060 0.13 1.52 9 NOTES:

46、 1. In case of conflict between the English and metric dimensions, the English dimensions control. 2. Dimensioning and tolerance per ANSI-Y14.5M-1982. 3. Dimensions A, A1, and L are measured with the package seating in JEDEC Seating Plane Gauge GS-3. 4. D and E1 dimensions include allowance for pack

47、age irregularities and lid misalignment. 5. E and eA measured with the leads constrained to be perpendicular to plane C. 6. eB measured at the lead tips with the leads unconstrained. 7. Pointed or rounded lead tips are preferred to ease insertion. 8. To facilitate automatic insertion, any raised irr

48、egularity on the top surface (step, mass, etc.) shall be symmetrical about the lateral and longitudinal package centerlines. 9. Metallization of closest approach (pad or lead) to package edge. FIGURE 1. Case outline Y - continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88532 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL C SHEET 9 DSCC FORM 2234 APR 97 Device type 01 Device type 01 Case outline X Y T, U, and Z Case outline X Y T, U, and Z Terminal number Termi