DLA SMD-5962-87735 REV B-1998 MICROCIRCUIT CMOS MICROPROCESSOR OPTIMIZED FOR DIGITAL SIGNAL PROCESSING MONOLITHIC SILICON《硅单片微处理器优化数字信号处理互补型金属氧化物半导体微电路》.pdf

《DLA SMD-5962-87735 REV B-1998 MICROCIRCUIT CMOS MICROPROCESSOR OPTIMIZED FOR DIGITAL SIGNAL PROCESSING MONOLITHIC SILICON《硅单片微处理器优化数字信号处理互补型金属氧化物半导体微电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-87735 REV B-1998 MICROCIRCUIT CMOS MICROPROCESSOR OPTIMIZED FOR DIGITAL SIGNAL PROCESSING MONOLITHIC SILICON《硅单片微处理器优化数字信号处理互补型金属氧化物半导体微电路》.pdf（30页珍藏版）》请在麦多课文档分享上搜索。

1、SMD-5962-87735 REV B m 9999976 0327949 773 m I REVISION I t DESCRIPTION Inactivate device type 02 for new design. Add device types 03 and 04. Alter electrical performance characteristics and associated waveforms. Editorial changes throughout. Add device types 05 and 06. Change minimum limits for dev

2、ice type 01, test numbers 1 O and 27 and minimum limits for device type 04, test numbers 41 and 62 in table I. Correct vendor CAGE number and vendor address. Editorial changes throughout. - tvn REV STATUS OF SHEETS PMlC N/A STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPAR

3、TMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC NIA DATE (YR-MO-DAI I APPROVED 89-04-24 - Michael A. Frye 98-06-01 Monica L. Poelking SHEET 12345678910 PREPAREDBY BBBB 11 1 13 12 DEFENSE SUPPLY CENTER COLUMBUS CHECKED BY COLUMBUS, OHIO 43216 Ray Monnin APPROVEDBY Michael A. Frye MICROCIRCUIT,

4、CMOS, MICROPROCESSOR OPTIMIZED FOR DIGITAL SIGNAL PROCESSING, MONOLITHIC SILICON DRAWING APPROVAL DATE 88-02-25 REVISION LEVEL B 1 “5 I 67268 I 5962-87735 CAGE CODE I SHEET 1 OF 29 DSCC FORM 2233 APR 97 5962-E316-98 DISTRIBUTION STATEMENT A Approved for public release; distribution is unlimited. Pro

5、vided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-87735 REV B W 9999996 0327950 Y95 m 1. SCOPE 1.1 ScoDe. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535,

6、appendix A. 1.2 Part or Identifvina Number (PIN). The complete PIN is as shown in the following example: 5962-35 f i 1 Drawing number Device type Case outline Lead finish (see 1.2.1) (see 1.2.2) (see 1.2.3) 1.2.1 Device tvDe(s). The device type(s) identify the circuit function as follows: Device tvD

7、e Generic number Circuit function O1 02 03 04 05 06 21 OOSG 2 1 OOTG 21 OOASG 2 1 OOATG 21 OOAUG 21 OOAVG Digital signal processor Digital signal processor Digital signal processor Digital signal processor Digital signal processor Digital signal processor Freauencv 6 MHz 8 MHz 8 MHz 1 O MHz 12 MHz 1

8、6 MHz 1.2.2 Case outlinek). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter DescriDtive desianator Terminals Packaae stvle X CMGA17-Pl O0 1 O0 Pin grid array 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum rat

9、inas. Supply voltage range -0.3 V dc to +7 V dc Input voltage -0.3 V dc to VCC + 0.3 V dc Output voltage swing . -0.3 V dc to VCC + 0.3 V dc Maximum power dissipation (PD) 0.750 W Storage temperature range -65“ C to +150“ C Lead temperature (soldering, 1 O seconds) . +300“C Thermal resistance, junct

10、ion-to-case (8JC) . See MIL-PRF-38535 Junction temperature (TJ) . +165“ C 1.4 Recommended oDeratina conditions. Operating supply voltage range (VCC) . +4.5 V dc to +5.5 V dc Case operating temperature range (TC) . -55“ C to +125“ C STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS 5962-87

11、735 COLUMBUS, OHIO 43216-5000 VSLG tUHM X34 APR 97 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-87735 REV B D 999999b 0327953 323 m 2. APPLICABLE DOCUMENTS 2.1 Government sDecification. standards, and handbooks. The following specificatio

12、n, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitatio

13、n. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-973 - Configuration Management. MIL-STD-1835 - Interface Standard For Microcircuit Case Outl

14、ines. HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 - List of Standard Microcircuit Drawings (SMDs). MIL-HDBK-780 - Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbin

15、s Avenue, Building 4D, Philadelphia, PA 191 1 1-5094.) 2.2 Order of orecedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless

16、 a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item reauirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non- JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacture

17、r Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL- PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This

18、QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “W or “QML certification mark in accordance wit

19、h MIL- PRF-38535 is required to identify when the QML flow option is used. 3.2 Desian. construction. and ohvsical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline. The case outline shall be in accordance w

20、ith 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure l. 3.2.3 Block diagram. The block diagram shall be as specified on figure 2. 3.2.4 Test circuit and waveforms. The test circuit and waveforms are as specified on figure 3. STANDARD MICROCIRCUIT DRA

21、WING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 4321 6-5000 DSCC FORM 2234 APR 97 I 5962-87735 REVISION LEVEL Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-87735 REV B m 999999b 0327952 268 m 3.3 Electrical Derformance characteristics.

22、Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test reauirements. The electrical test requirements shall be the subgroups specified in table II. The electrical te

23、sts for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufactureh PIN may also be marked as listed in MIL-HDBK-103 (see 6.6 herein). For packages where

24、marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.6 Certificate of comdiance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supp

25、ly in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A cert

26、ificate of conformance as required in MIL-PRF-38535, appendix Ashall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of chanae. Notification of change to DSCC-VA shall be required in accordance with MIL-PRF-38535, appendix A. 3.9 Verification and review. DSCC,

27、DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 4. QUALITY ASSURANCE PROVISIONS 4.1 SamDlina and insuection. Sampling and inspec

28、tion procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, metho

29、d 1015 of MIL-STD-883. (1) Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipati

30、on, as applicable, in accordance with the intent specified in test method 1 O1 5 Of MIL-STD-883. (2) TA = +125“C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discreti

31、on of the manufacturer. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS 5962-87735 COLUMBUS, OHIO 4321 6-5000 APR 97 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-TABLE I. Electrical Derformance characteristics. High level input voltag

32、e - 11 t Low level input voltage High level output voltage Low level output voltage - Three-state leakage current High level input current - 31 1 IOZH Vcc = maximum All 10 IOZL VCC = maximum All 1,2,3 10 IOZL VCC = maximum 01,02,03 1,2, 3 150 04,05,06 180 ICC VCC = maximum All 1,2,3 15 ICC VCC = max

33、imum o1 1,2,3 1 O0 130 VIN = Vcc maximum 5/ VIN = 0.0 v - 51 VIN = 0.0 v - 51 VIN = 0.0 v - 51 zl maximum clock rate 91 02,03 I 04 18 Three-state pull-up leakage current 71 I (power down) s/ I Supply current Supply current (dynamic) Symbol Conditions Device Group A Limits -55C HALT I .n IRQO-3 NOTE:

34、 The control signals are shown in relationship to the processor states in which they are recognized or asserted as defined by CLKIN. There is no implied relationship between m, TRAP, and 0-3. Control signals CLKIN RESET NOTE: The RESET signal determines the phase of the processor cycle. The processo

35、r starts from state 4 after the release of the RESET signal. RESET signal FIGURE 3. Test circuit and waveforms - Continued. STANDARD SIZE MICROCIRCUIT DRAWING A 5962-87735 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL SHEET B 20 APR 97 Provided by IHSNot for ResaleNo reprod

36、uction or networking permitted without license from IHS-,-,- SMD-5962-87735 REV B 9999996 0127969 561 H CLKIN - BR - BG xMxx “ NOTE: xMxx refers to PMAO-13, ES, m, WR, PMDA, DMAO-13, DMS , DMRD , and DMWR . Bus request negated - BR - BG NOTE: During RESET, the processor bus ignores the CLKIN signal

37、and therefore the bus requestlgrant signals operate asynchronously. Bus requestlgrant with RESET low FIGURE 3. Test circuit and waveforms - Continued. STANDARD SIZE MICROCIRCUIT DRAWING A 5962-87735 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL SHEET B 21 DSCC FORM 2234 APR

38、 97 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-FIGURE 3. Test circuit and waveforms - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-FIGURE 3. Test circuit and waveforms - Continued.

39、Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-PMA SMD-5962-87735 REV B W 9999996 0327972 056 W PMDA PMRD -7” I x W I I PMD FIGURE 3. Test circuit and waveforms - Continued. APR 97 Program memory read Provided by IHSNot for ResaleNo reproduction or

40、networking permitted without license from IHS-,-,-DMS DMRD 7-t DMA I t -“ J, I I t- DMACK DMD 64 li Data memory write FIGURE 3. Test circuit and waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 IA1 SIZE I 5962-87735 REVISION LEVEL SHEET B

41、25 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-87735 REV B m 999999b 0327974 929 m DMA -1 DMRD DMWR DMACK DMD Il Data memory read FIGURE 3. Test circuit and waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUM

42、BUS COLUMBUS, OHIO 43216-5000 /Al SIZE I 5962-87735 REVISION LEVEL SHEET B 26 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-II CLKOUT Data memory wait states extended with DMACK FIGURE 3. Test circuit and waveforms - Continued. APR 97 Provided by I

43、HSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SUD-5962-87735 REV B m 3999976 0127976 7TL m TABLE II. Electrical test reauirements. MIL-STD-883 test requirements Subgroups (in accordance with MIL-STD-883, method 5005, table I) Interim electrical parameters 1,7,9

44、 (method 5004) (method 5004) Final electrical test parameters 1*,2, 3, 7,8, 9, 10, 11 Group A test requirements 1,2,3,4,7,8,9,10,11 (method 5005) Groups C and D end-point 1,2,3,7,8,9,10,11 electrical parameters (method 5005) * PDA applies to subgroup l. 4.3 Qualitv conformance inspection. Quality co

45、nformance inspection shall be in accordance with method 5005 of MIL-STD-883 including groups A, B, C, and D inspections. The following additional criteria shall apply. 4.3.1 GrOUD A insmtion. a. Tests shall be as specified in table II herein. b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-8

46、83 shall be omitted. c. Subgroup 4 (CIN measurement) shall be measured only for the initial test and after process or design changes which d. Subgroups 7 and 8 tests shall verify the instruction set. The instruction set forms a part of the vendors test tape and may affect input capacitance. A minimu

47、m sample size of three devices with zero rejects shall be required. shall be maintained and available for review from the approved sources of supply. 4.3.2 Groups C and D insDections. a. End-point electrical parameters shall be as specified in table II herein. b. Steady-state life test conditions, m

48、ethod 1005 of MIL-STD-883. (1) Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissi

49、pation, as applicable, in accordance with the intent specified in test method 1005 of MIL-STD-883. (2) TA = +I 25“ C, minimum. (3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. 5. PACKAGING 5.1 Packaaina reauirements. The requirements for packaging shall be in accordance