DLA SMD-5962-87725 REV C-2012 MICROCIRCUIT DIGITAL HIGH-SPEED CMOS OCTAL D-TYPE FLIP-FLOP WITH MASTER RESET TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Delete vendor CAGE 27014. Change vendor CAGE 18714 to 34371. Editorial changes throughout. 90-10-10 Michael A. Frye B Make corrections to VCCfor ICC, IIN, and AC tests in table I. Add notes to figure 4, switching waveforms and test circuit. Updat

2、e the boilerplate to current requirements as specified in MIL-PRF-38535. Editorial changes throughout. jak 06-02-16 Thomas M. Hess C Update test condition of high and low level output voltage (VOHand VOL) to table I. Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. - LTG 12-0

3、6-22 Thomas M. Hess REV SHEET REV SHEET REV STATUS REV C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Greg A. Pitz DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL D

4、EPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY D.A. DiCenzo APPROVED BY Michael A. Frye MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, OCTAL D-TYPE FLIP-FLOP WITH MASTER RESET, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON DRAWING APPROVAL DATE 88-03-22 REVISION LEVEL C SIZE A CAGE CO

5、DE 67268 5962-87725 SHEET 1 OF 10 DSCC FORM 2233 APR 97 5962-E370-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87725 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 22

6、34 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-87725 01 R A Drawing

7、 number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54HCT273 Octal D-type flip-flop with master reset, TTL compatible inputs 1.2.2 Case outli

8、ne(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20 Dual-in-line 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ 2/ 3/

9、Supply voltage range (VCC) . -0.5 V dc to +7.0 V dc DC input voltage range (VIN) . -0.5 V dc to VCC + 0.5 V dc DC output voltage range (VOUT) -0.5 V dc to VCC+ 0.5 V dc Clamp diode current (IIK, IOK) 20 mA DC output current (per pin) (IOUT) 25 mA DC VCCor GND current (per pin) 50 mA Storage temperat

10、ure range (TSTG) -65C to +150C Maximum power dissipation (PD) . 500 mW 4/ Lead temperature (soldering, 10 seconds) . +260C Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Junction temperature (TJ) . +175C 1.4 Recommended operating conditions. Supply voltage range (VCC) . +4.5 V to +5.5 V

11、Case operating temperature range (TC) -55C to +125C Input voltage range (VIN) . 0.0 V dc to VCC Output voltage range (VOUT) 0.0 V dc to VCCInput rise or fall time (tr, tf) (VCC= 4.5 V) . 0 to 500 ns Minimum setup time, data to CP (ts): TC= +25C, VCC= 4.5 V . 20 ns TC= -55C and +125C, VCC= 4.5 V 30 n

12、s _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise specified, all voltages are referenced to ground. 3/ The limits for the parameters specified herein

13、 shall apply over the full specified VCCrange and case temperature range of -55C to +125C. 4/ For TC= +100C to +125C, derate linearly at 12 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87725 DLA LAND

14、 AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions - Continued. Minimum clock pulse width (tw1): TC= +25C, VCC= 4.5 V . 20 ns TC= -55C and +125C, VCC= 4.5 V 30 ns Minimum hold time, data to CP (th): TC= +25C, VCC= 4.5 V . 10 ns

15、 TC= -55C and +125C, VCC= 4.5 V 15 ns Minimum MR pulse width (tw2): TC= +25C, VCC= 4.5 V . 16 ns TC= -55C and TC= +125C, VCC= 4.5 V 24 ns Minimum removal time, MR to CP (tREM): TC= +25C, VCC= 4.5 V . 20 ns TC= -55C and +125C, VCC= 4.5 V 30 ns Maximum clock frequency (fMAX): TC= +25C, VCC= 4.5 V . 25

16、 MHz TC= -55C and +125C, VCC= 4.5 V 16 MHz 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are t

17、hose cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case

18、 Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue,

19、Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents cited in the solicitation or contract. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION

20、 (JEDEC) JEDEC Standard No. 7 - Standard for Description of 54/74HCXXXXX and 54/74HCTXXXXX Advanced High-Speed CMOS Devices. (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10thStreet, Suite 240-S Arlington, VA 22201

21、). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. Provided by

22、 IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87725 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirement

23、s shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certifi

24、cation to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. The

25、se modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physica

26、l dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3

27、Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3.3 Electrical performance characteristics

28、. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical

29、tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is

30、not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall

31、 be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (s

32、ee 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certifi

33、cate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and re

34、view. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo re

35、production or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87725 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Test conditions 1/ -55C TC +125C

36、 unless otherwise specified VCCGroup A subgroups Limits Unit Min Max High level output voltage VOHVIN= VIH= 2.0 V or VIL= 0.8 V IOH= -20 A 4.5 V 1, 2, 3 4.4 V VIN= VIH= 2.0 V or VIL= 0.8 V IOH= -4.0 mA 4.5 V 3.7 Low level output voltage VOLVIN= VIH= 2.0 V or VIL= 0.8 V IOL= +20 A 4.5 V 1, 2, 3 0.1 V

37、 VIN= VIH= 2.0 V or VIL= 0.8 V IOL= +4.0 mA 4.5 V 0.4 High level input voltage VIH2/ 4.5 V 1, 2, 3 2.0 V Low level input voltage VIL2/ 4.5 V 1, 2, 3 0.8 V Input capacitance CINSee 4.3.1c, TC= +25C GND 4 10 pF Quiescent supply current ICCVIN= VCCor GND 5.5 V 1, 2, 3 160 A Additional quiescent supply

38、current, TTL inputs ICC3/ For any one input, VIN= 2.4 V or 0.5 V For all other inputs, VIN= VCCor GND 5.5 V 1, 2, 3 3.0 mA Input leakage current IINVIN= VCCor GND 5.5 V 1, 2, 3 1.0 A Functional tests See 4.3.1d 7, 8 Propagation delay time, CP to Qn tPHL1, tPLH1 CL= 50 pF See figure 4 4.5 V 9 36 ns 4

39、.5 V 10, 11 54 ns Propagation delay time, MR to Qn tPHL24.5 V 9 35 ns 4.5 V 10, 11 53 ns Transition time tTLH, tTHL 4/ 4.5 V 9 15 ns 4.5 V 10, 11 22 ns 1/ For power supply of 5 V 10 percent, the worst case output voltages (VOHand VOL) occur for high-speed CMOS at 4.5 V. Thus, the 4.5 V values should

40、 be used when designing with this supply. Worst cases VIHand VILoccur at VCC= 5.5 V and 4.5 V respectively. 2/ VIHand VILtests are not required if applied as a forcing function for VOHor VOLtest. 3/ Guaranteed, if not tested, to the specified limits in table I. 4/ Transition times (tTLHand tTHL), if

41、 not tested, shall be guaranteed to the specified limits in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87725 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 22

42、34 APR 97 Device type 01 Case outline R Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MR Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND CP Q4 D4 D5 Q5 Q6 D6 D7 Q7 VCCFIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license

43、 from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87725 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 Inputs Outputs MR CP Dn Qn L X X L H H H H L L H X X Q0 L = Low voltage level H = High voltage level = Low-to-high transition of the clock X =

44、Dont care Q0 = The level of Q before the indicated steady-state input conditions were established FIGURE 2. Truth table. FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87725 DLA LAND

45、 AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 8 DSCC FORM 2234 APR 97 NOTES: 1. CL= 50 pF or equivalent (includes test jig and probe capacitance). 2. Input signal from pulse generator: VIN= 0.0 V to 3.0 V; PRR 1 MHz; ZO= 50; tr= 6.0 ns; tf= 6.0 ns; trand tfshall be measured from 0.3

46、 V to 2.7 V and from 2.7 V to 0.3 V, respectively; duty cycle = 50 percent. 3. The outputs are measured one at a time with one transition per measurement. FIGURE 4. Switching waveforms and test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,

47、-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87725 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 9 DSCC FORM 2234 APR 97 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screen

48、ing shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and po