DLA SMD-5962-80003 REV H-2012 MICROCIRCUIT DIGITAL 6-BIT N-CHANNEL SINGLE-CHIP MICROPROCESSOR MONOLITHIC SILICON.pdf

《DLA SMD-5962-80003 REV H-2012 MICROCIRCUIT DIGITAL 6-BIT N-CHANNEL SINGLE-CHIP MICROPROCESSOR MONOLITHIC SILICON.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-80003 REV H-2012 MICROCIRCUIT DIGITAL 6-BIT N-CHANNEL SINGLE-CHIP MICROPROCESSOR MONOLITHIC SILICON.pdf（27页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Pages 1, 2, 3, 4, 14, 15, 16, editorial changes. Pages 5, 6, 7, 8, symbol corrections. Page 18, added vendor. 81-12-09 M. A. Frye B Add device type 03. Type 02 inactive for new design: Use MIL-M-38510/52002 for case Q. Type 01 and new type 03 are

2、 still active. 83-04-06 M. A. Frye C Add device types 04 and 05. 84-10-31 M. A. Frye D Case temperature to +125C. Add LCC package, electrical test improvements. 85-11-12 M. A. Frye E Change to military drawing format. Add device type 06, changes to 1.4, add vendor CAGE number 66958, delete vendor CA

3、GE number 34335, changes to table I, changes to figures 1, 2, and 3. Editorial changes throughout. Change Code Ident. No. to 67268. 87-12-17 M. A. Frye F Update boilerplate to MIL-PRF-38535 requirements. Correct drawing title to indicate device function. - CFS 03-06-11 Thomas M. Hess G Correct marki

4、ng requirements in 3.5. Update boilerplate in accordance with MIL-PRF-38535 requirements. - PHN. 05-03-23 Thomas M. Hess H Add device type 06 to case outlines X and Q in figure 2. Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. - LTG 12-12-19 Thomas M. Hess REV SHEET REV H H

5、 H H H H H H H H H H SHEET 15 16 17 18 19 20 21 22 23 24 25 26 REV STATUS REV H H H H H H H H H H H H H H OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Ray Monnin DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING T

6、HIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY Charles Reusing APPROVED BY Michael. A. Frye MICROCIRCUIT, DIGITAL, 6-BIT N-CHANNEL SINGLE-CHIP MICROPROCESSOR, MONOLITHIC SILICON DRAWING APPROVAL DATE 80-07-21 REVISION LEVEL H SIZE A

7、CAGE CODE 67268 80003 SHEET 1 OF 26 DSCC FORM 2233 APR 97 5962-E444-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 80003 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL H SHEET 2 DSCC FORM 2234

8、APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 80003 01 X A Drawing number

9、Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Frequency Circuit function 01 Z8001 4.0 MHz 16-Bit N-channel single-chip microprocessor 02 Z8002 4.0 MHz 16-Bit N-cha

10、nnel single-chip microprocessor 03 Z8001A 6.0 MHz 16-Bit N-channel single-chip microprocessor 04 Z8001B 10.0 MHz 16-Bit N-channel single-chip microprocessor 05 Z8002B 10.0 MHz 16-Bit N-channel single-chip microprocessor 06 Z8002A 6.0 MHz 16-Bit N-channel single-chip microprocessor 1.2.2 Case outline

11、(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style Q GDIP1-T40 or CDIP2-T40 40 Dual-in-line U CQCC1-N52 52 Square leadless chip carrier X See figure 1 48 Dual-in-line Y CQCC1-N44 44 Square leadless chip carrier Z C

12、QCC1-N68 68 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range with respect to ground (VCC) -0.3 V dc to +7.0 V dc Storage temperature range -65C to +150C Maximum power dissipation (PD) (per

13、 device) 2.2 W Lead temperature (soldering, 5 seconds) . +270C Maximum junction temperature (TJ) . +150C Thermal resistance, junction-to-case (JC): Case X 14C/W Cases Q, U, Y, Z See MIL-STD-1835 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDAR

14、D MICROCIRCUIT DRAWING SIZE A 80003 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL H SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Minimum high level input voltage (VIH): Logic inputs +2.2 V dc to VCC+ 0.3 V dc C

15、lock input VCC 0.4 V dc to VCC+ 0.3 V dc RESET (NMI) 2.4 V dc to VCC+ 0.3 V dc Maximum low level input voltage (VIL): Logic inputs -0.3 V dc to +0.8 V dc Clock input -0.3 V dc to +0.45 V dc Frequency of operation: 01, 02 . 0.5 MHz to 4.0 MHz 03, 06 . 0.5 MHz to 6.0 MHz 04, 05 . 0.5 MHz to 10.0 MHz C

16、ase operating temperature range (TC) . -55C to +125C Clock rise time (tr): 01, 02 . 20 ns maximum 03, 06 . 15 ns maximum 04, 05 . 10 ns maximum Clock fall time (tf): 01, 02 . 20 ns maximum 03, 06 . 10 ns maximum 04, 05 . 15 ns maximum 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards,

17、and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated C

18、ircuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-7

19、80 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the t

20、ext of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. Provided by IHSNot for ResaleNo reproduction or networking permitted without li

21、cense from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 80003 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL H SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class

22、 level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance wit

23、h the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. T

24、hese modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be

25、as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein and on figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Logic functions. The logic functions shall be as specif

26、ied on figure 3. 3.2.4 Timing waveforms. The timing waveforms shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperat

27、ure range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the P

28、IN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A complianc

29、e indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance.

30、 A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manuf

31、acturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of chan

32、ge. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable requi

33、red documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 80003 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISI

34、ON LEVEL H SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Test conditions -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Group A subgroups Device type Limits Unit Min Max Clock input low voltage VIL1Driven by external clock generator. 1, 2, 3 A

35、ll -0.3 1/ 0.45 V Clock input high voltage VIH11, 2, 3 All VCC 0.4 VCC+ 0.3 1/ V Input low voltage VIL21, 2, 3 All -0.3 1/ 0.8 V Input high voltage VIH21, 2, 3 All 2.4 VCC+ 0.3 1/ V Reset input high voltage (NMI) VIH31, 2, 3 All 2.4 VCC+ 0.3 1/ V High level output voltage all outputs VOHIOH= -250 A

36、VCC= 4.5 V 1, 2, 3 All 2.4 V Low level output voltage all outputs VOLIOL= +2.0 mA VCC= 4.5 V 1, 2, 3 All 0.4 V High-impedance (off-state) output current (High) (In Float) IZHVIN= 2.4 V VCC= 5.5 V 1, 2, 3 All 10 +10 A High-impedance (off-state) output current (Low) (In Float) IZLVIN= 0.4 V VCC= 5.5 V

37、 1, 2, 3 All 10 +10 A High level input current (input and bi-directional) IIHVIN= 2.4 V VCC= 5.5 V 1, 2, 3 All -10 +10 A Low level input current (input and bi-directional) IILVIN= 0.4 V VCC= 5.5 V 1, 2, 3 All -10 +10 A Low level input current (SEGT) IILS0.4 V VIN 2.4 V 4.5 V VCC 5.5 V 1, 2, 3 01, 03

38、, 04 +200 A Supply current ICCVCC= 5.5 V 1, 2, 3 All 400 mA Functional tests See 4.3.1c 7, 8 All See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 80003 DLA LAND AND MARITIME COLUMBUS,

39、 OHIO 43218-3990 REVISION LEVEL H SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Test conditions -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Group A subgroups Device type Limits Unit Min Max Clock pulse tcycSee figure 4. See Refe

40、rence No. 1 2/ CL= 50 pF to 100 pF 10%, all outputs 9, 10, 11 01, 02 250 2000 ns 03, 06 165 2000 04, 05 100 2000 Clock pulse width (Low) tPWL1See figure 4. See Reference No. 2 2/ CL= 50 pF to 100 pF 10%, all outputs 9, 10, 11 01, 02 105 ns 03, 06 70 04, 05 40 Clock pulse width (High) tPWH1See figure

41、 4. See Reference No. 3 2/ CL= 50 pF to 100 pF 10%, all outputs 9, 10, 11 01, 02 105 ns 03, 06 70 04, 05 40 Clock to segment number valid TdC(SNv) 3/ 4/ See figure 4. See Reference No. 6 2/ CL= 50 pF to 100 pF 10%, all outputs 9, 10, 11 01 130 ns 03 110 04 90 Clock to segment number not valid TdC(SN

42、n) 4/ See figure 4. See Reference No. 7 2/ CL= 50 pF to 100 pF 10%, all outputs 9, 10, 11 01 20 ns 03 10 04 0 Clock to bus float TdC(Bz) 1/ See figure 4. See Reference No. 8 2/ CL= 50 pF to 100 pF 10%, all outputs 9, 10, 11 01, 02 65 ns 03, 06 55 04, 05 50 Clock to address valid TdC(A) See figure 4.

43、 See Reference No. 9 2/ CL= 50 pF to 100 pF 10%, all outputs 9, 10, 11 01, 02 100 ns 03, 06 75 04, 05 65 Clock to address float TdC(Az) 1/ See figure 4. See Reference No. 10 2/ CL= 50 pF to 100 pF 10%, all outputs 9, 10, 11 01, 02 65 ns 03, 06 55 04, 05 50 Address valid to data in required valid TdA

44、(DR) See figure 4. See Reference No. 11 2/ CL= 50 pF to 100 pF 10%, all outputs 9, 10, 11 5/ 01, 02 475 ns 03, 06 305 04, 05 180 Data to CLK setup time TsDR(C) See figure 4. See Reference No. 12 2/ CL= 50 pF to 100 pF 10%, all outputs 9, 10, 11 01, 02 30 ns 03, 06 20 04, 05 10 See footnotes at end o

45、f table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 80003 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL H SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Conti

46、nued. Test Symbol Test conditions -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Group A subgroups Device type Limits Unit Min Max DS to address active TdDS(A) See figure 4. See Reference No. 13 2/ CL= 50 pF to 100 pF 10%, all outputs 9, 10, 11 5/ 01, 02 80 ns 03, 06 45 04, 05 20 Clock t

47、o data out valid TdC(DW) See figure 4. See Reference No. 14 2/ CL= 50 pF to 100 pF 10%, all outputs 9, 10, 11 01, 02 100 ns 03, 06 75 04, 05 60 Data in to DS hold time ThDR(DS) See figure 4. See Reference No. 15 2/ CL= 50 pF to 100 pF 10%, all outputs 9, 10, 11 01, 02 0 ns 03, 06 0 04, 05 0 Data out

48、 valid to DS delay TdDW(DS) See figure 4. See Reference No. 16 2/ CL= 50 pF to 100 pF 10%, all outputs 9, 10, 11 5/ 01, 02 295 ns 03, 06 195 04, 05 110 Address valid to MREQ delay TdA(MR) See figure 4. See Reference No. 17 2/ CL= 50 pF to 100 pF 10%, all outputs 9, 10, 11 5/ 01, 02 55 ns 03, 06 35 04, 05 20 Clock to MREQ delay TdC(MR) See figure 4. See Reference No. 18 2/ CL= 50 pF to 100 pF 10%, all outputs 9, 10, 11 01, 02 80 ns 03, 06 70 04, 05 50 MREQ width (High) TwMRh See figure 4. See Reference No. 19 2/ CL= 50 pF to 100 pF