DLA DSCC-VID-V62 07619-2013 MICROCIRCUIT LINEAR HEX INVERTERS MONOLITHIC IC SILICON.pdf

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1、 REVISIONSLTR DESCRIPTION DATE APPROVEDPrepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Original date o

2、f drawing July 10, 2013 CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, LINEAR, HEX INVERTERS, MONOLITHIC SILICON APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/07619 REV PAGE 1 OF 10 AMSC N/A 5962-V068-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without

3、 license from IHSDLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07619 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance Hex inverters microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item D

4、rawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/07619 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1

5、) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74AHCU04 -EP Hex Inverters1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 14 JEDEC MO-153 Plastic Small Outline 1.2.3 Lead finishes.

6、The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without licen

7、se from IHSDLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07619 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to 7.0 V Input voltage range (VI) . -0.5 V to 7.0 V 2/ Output voltage range (VO) . -0.5 V to VCC+ 0.5 V 2/ Input clamp current

8、 (IIK) (VI 0) . -20 mA Output clamp current (IOK) (VO 0 or VO= 0 to VCC) 20 mA Continuous output current (IO) (VO= 0 to VCC) 25 mA Continuous current through VCCor GND . 50 mA Package thermal impedance (JA) . 113C/W 3/ Storage temperature range (TSTG) . -60C to 150C 1.4 Recommended operating conditi

9、ons. 4/ 5/ Supply voltage range (VCC) . 2.0 V to 5.5 V Minimum high level input voltage (VIH): VCC= 2.0 V 1.7 V VCC= 3.0 V 2.4 V VCC= 5.5 V 4.4 V Maximum low level input voltage (VIL): VCC= 2.0 V 0.3 V VCC= 3.0 V 0.6 V VCC= 5.5 V 1.1 V Input voltage (VI) . 0.0 V to VCCOutput voltage (VO) . 0.0 V to

10、VCCMaximum high level output current (IOH): VCC= 2.0 V -50 A VCC= 3.3 0.3 V -4 mA VCC= 5.0 0.5 V -8 mA Maximum low level output current (IOL): VCC= 2.0 V 50 A VCC= 3.3 0.3 V 4 mA VCC= 5.0 0.5 V 8 mA Operating free-air temperature range (TA) -55C to +125C 1/ Stresses beyond those listed under “absolu

11、te maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extend

12、ed periods may affect device reliability. 2/ The input and output negative voltage ratings may be exceeded if the input and output current ratings are observed. 3/ The package thermal impedance is calculated in accordance with JESD 51-7. 4/ Use of this product beyond the manufacturers design rules o

13、r stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 5/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. Provided by IHSNot for Resale-,-,-DLA

14、LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07619 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surfa

15、ce Mount Packages (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201-2107). 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers

16、part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical ch

17、aracteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.

18、1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Function table. The function table shall be as shown in figure 3. 3.5.4 Logic diagram. The logic diagram shall be as shown in figure 4.

19、3.5.5 Load circuit and voltage waveforms. The load circuit and voltage waveforms shall be as shown in figure 5. Provided by IHSNot for Resale-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07619 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Sym

20、bol Conditions 2/ VCCTemperature, TADevice type Limits Unit Min Max High level output voltage VOHIOH= -50 A 2.0 V 25C, -55C to 125C All 1.8 V 3.0 V 2.7 4.5 V 4.0 IOH= -4 mA 3.0 V 25C 2.58 -55C to 125C 2.3 IOH= -8 mA 4.5 V 25C 3.94 -55C to 125C 3.5 Low level output voltage VOLIOL= 50 A 2.0 V 25C All

21、0.1 V -55C to 125C 0.2 3.0 V 25C 0.1 -55C to 125C 0.3 4.5 V 25C 0.1 -55C to 125C 0.5 IOL= 4 mA 3.0 V 25C 0.26 -55C to 125C 0.5 IOL= 8 mA 4.5 V 25C 0.26 -55C to 125C 0.5 Input current IIVI= VCCor GND 0 to 5.5 V 25C All 0.1 A -55C to 125C 1.0 Quiescent supply current ICCVI= VCCor GND IO= 0 A 5.5 V 25C

22、 All 2.0 A -55C to 125C 20.0 Input capacitance CIVI= VCCor GND 5 V 25C, -55C to 125C All 10 pF Power dissipation capacitance CpdNo load, f = 1 MHz 25C All 7.3 TYP Switching characteristics Propagation delay time, A to Y tPLHCL= 50 pF See figure xx 3.3 0.3 V 25C All 1 10.6 ns -55C to 125C 1 14 5 0.5

23、V 25C 1 7 -55C to 125C 1 11 tPHLCL= 50 pF See figure xx 3.3 0.3 V 25C All 1 10.6 ns -55C to 125C 1 14 5 0.5 V 25C 1 7 -55C to 125C 1 11 See footnote at end of table. Provided by IHSNot for Resale-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07619 REV PAGE 6 TABLE

24、I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions 3/ Limits Unit Min TYP Max Noise characteristics 4/ Quiet output, maximum dynamic VOLVOL(P)0.5 V Quiet output, minimum dynamic VOL(V) OL(V)-0.5 Quiet output, minimum dynamic VOH OH(V)4.3 High level dynamic input vo

25、ltage VIH(D)VIH(D)4 Low level dynamic input voltage VIH(D) IL(D)1 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and al

26、l parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Over operating temperature range (unless otherwise noted). 3/ VCC= 5 V, CL= 50 pF, TA= 25C. 4/ Characterists are for surface mount packages

27、only. Provided by IHSNot for Resale-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07619 REV PAGE 7 Case X Dimensions Symbol Millimeters Symbol Millimeters Min Max Min Max A 1.20 E 4.30 4.50 A1 0.05 0.15 E1 6.20 6.60 b 0.19 0.30 e 0.65 BSC c 0.15 NOM L 0.50 0.75 D 4

28、.90 5.10 NOTES: 1. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. This drawing is subject to change without notice. 3. Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 ea

29、ch side. 4. Body width does not include interlead flash. Interlead flash shall not exceed 0.25 each side. 5. Falls within JEDEC MO-153. FIGURE 1. Case outline. SEATINGPLANESEEDETAIL AbD17814EE1AA1e0.25(.010)c0-8LDETAIL AGAGEPLANEM0.10(.004)0.10(.004)Provided by IHSNot for Resale-,-,-DLA LAND AND MAR

30、ITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07619 REV PAGE 8 Case outline X Terminal number Terminal symbol Terminal number Terminal symbol 1 1A 14 VCC2 1Y 13 6A 3 2A 12 6Y 4 2Y 11 5A 5 3A 10 5Y 6 3Y 9 4A 7 GND 8 4Y FIGURE 2. Terminal connections. (Each Inverter) Input A Output Y H

31、L L H FIGURE 3. Function table. FIGURE 4. Logic diagram. YAProvided by IHSNot for Resale-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07619 REV PAGE 9 NOTES: 1. CLincludes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that

32、 the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO= 50 , tr

33、3 ns, tf 3 ns. 4. The output are measured one at a time, with one transition per measurement. 5. All parameters and waveforms are not applicable to all devices. FIGURE 5. Load circuit and voltage waveforms tPZLtPLZtPHZtPZHVOLVOHV0 VOUT-OF-PHASEOUTPUTtPLHtPHLtPLHtPHLVOH0 VIN-PHASEOUTPUTVOLINPUT50% VV

34、OHVOL50% VCC0 VtwtsuthDATAINPUTOUTPUTCONTROLCLFROM OUTPUTUNDER TESTOPENINPUTTIMINGINPUTCCCCOUTPUTWAVEFORM 1S1 AT VOUTPUTWAVEFORM 2S1 AT GNDSEE NOTE 250% VCC50% VCCSEE NOTE 1VCCGND+0.3 VOLCCSEE NOTE 2S1LOAD CIRCUIT FOR3-STATE AND OPEN-DRAIN OUTPUTSFROM OUTPUTUNDER TESTCLTEST POINTSEE NOTE 1LOAD CIRCU

35、IT FORTOTEM-POLE OUTPUTSVOLTAGE WAVEFORMSSETUP AND HOLD TIMESVOLTAGE WAVEFORMSPULSE DURATION-0.3 VOHVOLTAGE WAVEFORMSPROPAGATION DELAY TIMESINVERTING AND NONINVERTING OUTPUTSVOLTAGE WAVEFORMSENABLE AND DISABLE TIMESLOW AND HIGH-LEVEL ENABLING= 1 kL0 V0 V0 VVTEST S1tPLH/tPHLOPENtPLZ/tPZLtPHZ/tPZHVGND

36、CCVCCOPEN DRAINRVV50% VCCCCVCC50% VCC50% VCCVCC50% VCCVCC50% VCCVCCProvided by IHSNot for Resale-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07619 REV PAGE 10 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all i

37、nspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservati

38、on, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The

39、data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested so

40、urce(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current sources of supply at http:/www.landandmaritime.dla.mil/Programs/Smcr/. Vendor item drawing adminis

41、trative control number 1/ Device manufacturer CAGE code Vendor part number Top Side Marking V62/07619-01XE 01295 SN74AHCU04MPWREP AHCU04M 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for Resale-,-,-