DLA DSCC-VID-V62 05617 REV B-2012 MICROCIRCUIT DIGITAL-LINEAR WIDE INPUT SYNCHRONOUS BUCK CONTROLLER MONOLITHIC SILICON.pdf
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1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Add JESD51-5 information to paragraph 2. Add sentence to note 2 as specified under figure 1. Update boilerplate paragraphs to current requirements. - ro 11-08-15 C. SAFFLE B Under the SS/SD pin, delete 0.7 V and replace with 0.85 V as specified on figure 3.
2、 - ro 12-03-30 C. SAFFLE CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV B B B B B B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 11 12 1
3、3 14 15 PMIC N/A PREPARED BY RICK OFFICER DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHECKED BY TOM HESS TITLE MICROCIRCUIT, DIGITAL-LINEAR, WIDE INPUT SYNCHRONOUS BUCK CONTROLLER, MONOLITHIC SILICON 05-09-19 APPROVED BY RAYMOND MONNIN SIZE A CODE IDEN
4、T. NO. 16236 DWG NO. V62/05617 REV B PAGE 1 OF 15 AMSC N/A 5962-V038-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05617 REV B PAGE 2 1. SCOPE 1.1 Scope. This
5、 drawing documents the general requirements of a high performance wide input synchronous buck controller microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item dra
6、wing establishes an administrative control number for identifying the item on the engineering documentation: V62/05617 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 TPS40055-EP Wide input
7、 synchronous buck controller sources/sinks output current 02 TPS40054-EP Wide input synchronous buck controller sources output current only 03 TPS40057-EP Wide input synchronous buck controller sources/sinks output current with VOUTprebiased before controller is enabled 1.2.2 Case outline(s). The ca
8、se outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 16 MO-153 Plastic small outline package with thermal pad 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Mat
9、erial A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05617 REV B PAGE 3
10、1.3 Absolute maximum ratings. 1/ Input voltage range (VIN) : VINpin 45 V VFB, SS, SYNC pins -0.3 V to 6 V SW pin . -0.3 V to 45 V SW pin, transient 50 ns . -2.5 V KFF pin, with IIN(max)= -5 mA . -0.3 V to 11 V Output voltage range (VOUT) for COMP, RT, and SS pins -0.3 V to 6 V Input current (IIN) fo
11、r KFF pin . 5 mA Output current (IOUT) for RT pin 200 A Operating junction temperature range (TJ) -55C to +140C Storage temperature range (TSTG) -55C to +150C 2/ Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds . +260C Thermal resistance, junction to case (JC) . 26.6C/W Thermal resistanc
12、e, junction to ambient (JA) 36.5C/W 3/ 4/ Thermal resistance, junction to bottom of thermal pad (JP) 2.1C/W 3/ Junction to top thermal parameter (JT) . 0.848C/W 3/ 4/ 1.4 Recommended operating conditions. 5/ Input voltage range (VIN) . 8 V to 40 V Operating free-air temperature range (TA) . -55C to
13、+125C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Expos
14、ure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Long term high temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. 3/ See technical brief SLMA002 Power pad thermally enha
15、nced package. 4/ Tested in accordance with the thermal metric definitions of EIA/JESD51-5. 5/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond
16、the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05617 REV B PAGE 4 2. APPLICABLE DOCUMENTS JEDEC Solid State Technology Association JEDEC PUB 95
17、 - Registered and Standard Outlines for Semiconductor Devices JESD51-5 - Extension of Thermal Test Board Standards for Packages with Direct Thermal Attachment Mechanisms (Applications for copies should be addressed to the JEDEC Office, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201-2107 or
18、 online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The
19、 unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, c
20、onstruction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Logic
21、diagram. The logic diagram shall be as shown in figure 3. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05617 REV B PAGE 5 TABLE I. Electrical performance charac
22、teristics. 1/ Test Symbol Conditions 2/Temperature, TADevice type Limits Unit Min Max Input supply section Input voltage range VIN-55C to +125C 01,02,03 8 40 V Operating current section Quiescent current IDDOutput drivers not switching, VFB 0.75 V -55C to +125C 01,02,03 3.3 mA BP5 section Output vol
23、tage VBP5IOUT 1 mA -55C to +125C 01,02,03 4.7 5.3 V Oscillator/ramp generator section 3/ Accuracy fOSC8 V VIN 40 V -55C to +125C 01,02,03 465 585 kHz PWM ramp voltage 4/ VRAMPVPEAK VVAL-55C to +125C 01,02,03 2 typical V High level input voltage, SYNC pin VIH-55C to +125C 01,02,03 2 5 V Low level inp
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