BS DD IEC TS 62215-2-2007 Integrated circuits - Measurement of impulse immunity - Synchronous transient injection method《集成电路 脉冲抗扰度的测量 同步瞬时注射法》.pdf

《BS DD IEC TS 62215-2-2007 Integrated circuits - Measurement of impulse immunity - Synchronous transient injection method《集成电路 脉冲抗扰度的测量 同步瞬时注射法》.pdf》由会员分享，可在线阅读，更多相关《BS DD IEC TS 62215-2-2007 Integrated circuits - Measurement of impulse immunity - Synchronous transient injection method《集成电路 脉冲抗扰度的测量 同步瞬时注射法》.pdf（28页珍藏版）》请在麦多课文档分享上搜索。

1、 g49g50g3g38g50g51g60g44g49g42g3g58g44g55g43g50g56g55g3g37g54g44g3g51g40g53g48g44g54g54g44g50g49g3g40g59g38g40g51g55g3g36g54g3g51g40g53g48g44g55g55g40g39g3g37g60g3g38g50g51g60g53g44g42g43g55g3g47g36g58Part 2: Synchronous transient injection methodICS 31.200Integrated circuits Measurement of impulse

2、immunity DRAFT FOR DEVELOPMENTDD IEC/TS 62215-2:2007DD IEC/TS 62215-2:2007This Draft for Development was published under the authority of the Standards Policy and Strategy Committee on 30 November 2007 BSI 2007ISBN 978 0 580 55691 3to withdraw it. Comments should be sent to the Secretary of the resp

3、onsible BSI Technical Committee at British Standards House, 389 Chiswick High Road, London W4 4AL.The UK participation in its preparation was entrusted to Technical Committee EPL/47, Semiconductors.A list of organizations represented on this committee can be obtained on request to its secretary.This

4、 publication does not purport to include all the necessary provisions of a contract. Users are responsible for its correct application.Amendments issued since publicationAmd. No. Date Commentsresponsible for its conversion to an international standard. A review of this publication will be initiated

5、not later than 3 years after its publication by the international organization so that a decision can be taken on its status. Notification of the start of the review period will be made in an announcement in the appropriate issue of Update Standards.According to the replies received by the end of th

6、e review period, the responsible BSI Committee will decide whether to support the conversion into an international Standard, to extend the life of the Technical Specification or National forewordThis Draft for Development is the UK implementation of IEC/TS 62215-2:2007.This publication is not to be

7、regarded as a British Standard.It is being issued in the Draft for Development series of publications and is of a provisional nature. It should be applied on this provisional basis, so that information and experience of its practical application can be obtained.Comments arising from the use of this

8、Draft for Development are requested so that UK experience can be reported to the international organization IEC/TS 62215-2Edition 1.0 2007-09TECHNICAL SPECIFICATIONIntegrated circuits Measurement of impulse immunity Part 2: Synchronous transient injection method DD IEC/TS 62215-2:2007DD IEC/TS 62215

9、-2:2007CONTENTS INTRODUCTION.4 1 Scope.5 2 Normative references .5 3 Terms and definitions .5 4 General 6 4.1 Introduction .6 4.2 Measurement philosophy.6 4.3 Set-up concept 7 4.4 Response signal7 4.5 Coupling networks 8 4.5.1 General 8 4.5.2 Design of coupling networks .8 4.5.3 Coupling network for

10、 the ground/ Vsspin(s) 8 4.5.4 Coupling network for the supply/ Vddpin(s) .9 4.5.5 Coupling network for the I/O pin(s) 11 4.5.6 Coupling network for the reference pins.11 4.5.7 Coupling network verification.12 4.6 Test circuit board 12 4.6.1 General .12 4.6.2 IC pin loading / termination12 4.6.3 Pow

11、er supply requirements .13 4.7 IC specific considerations13 4.7.1 IC supply voltage.13 4.7.2 IC decoupling 13 4.7.3 Activity of IC13 4.7.4 Guidelines for IC stimulation13 4.7.5 IC monitoring.13 4.7.6 IC stability over time13 5 Test conditions .14 5.1 Default test conditions.14 5.1.1 General .14 5.1.

12、2 Ambient conditions 14 5.1.3 Ambient temperature .14 5.2 Impulse immunity of the test set-up .14 6 Test set-up .14 6.1 General .14 6.2 Test equipment .15 6.3 Set-up explanation 15 6.4 Explanation of signal relations.16 6.5 Calculation of time step and number of measurements to be conducted 16 6.6 T

13、est procedure 17 6.7 Monitoring check .17 6.8 System verification 17 DD IEC/TS 62215-2:2007DD IEC/TS 62215-2:2007 2 7 Test report18 7.1 General .18 7.2 Immunity limits or levels 18 7.3 Performance classes .18 7.4 Interpretation and comparison of results18 Annex A (informative) Flow chart of the soft

14、ware used in a microcontroller 19 Annex B (informative) Flow chart for the set-up control S/W (bus control program) 20 Annex C (informative) Test board requirements .21 Bibliography25 Figure 1 Synchronous transient injection immunity methodology waveforms 7 Figure 2 Test set-up diagram for synchrono

15、us transient injection immunity testing.8 Figure 3 Circuit diagram of the coupling network for ground/ Vsspin(s) of an IC .9 Figure 4 Method to impose synchronous transient injection into ground/ Vsspin(s) .9 Figure 5 Circuit diagram of the coupling network for supply/ Vddpin(s) of an IC 10 Figure 6

16、 Method to impose synchronous transient injection into supply/ Vddpin(s) 10 Figure 7 Method to impose synchronous transient injection into I/O pins11 Figure 8 Measurement set-up for synchronous transient injection 14 Figure 9 The waveforms (not in scale) appearing in the test set-up16 Figure A.1 Tes

17、t code flow chart19 Figure B.1 Test measurement flow chart 20 Figure C.1 Typical test board topology.24 Table 1 IC pin loading recommendations .12 Table C.1 Position of vias over the board.21 DD IEC/TS 62215-2:2007DD IEC/TS 62215-2:2007 3 INTRODUCTION In future standards, test methods and measuremen

18、t procedures will be given for transient immunity of integrated circuits: ESD pulse with resemblance to IEC 61000-4-2; EFT pulse with resemblance to IEC 61000-4-4; Surge pulse with resemblance to IEC 61000-4-5. DD IEC/TS 62215-2:2007DD IEC/TS 62215-2:2007 4 INTEGRATED CIRCUITS MEASUREMENT OF IMPULSE

19、 IMMUNITY Part 2: Synchronous transient injection method 1 Scope IEC/TS 62215-2, which is a technical specification, contains general information and definitions on the test method to evaluate the immunity of integrated circuits (ICs) against fast conducted synchronous transient disturbances. This i

20、nformation is followed by a description of measurement conditions, test equipment and test set-up as well as the test procedures and the requirements on the content of the test report. The objective of this technical specification is to describe general conditions to obtain a quantitative measure of

21、 immunity of ICs establishing a uniform testing environment. Critical parameters that are expected to influence the test results are described. Deviations from this specification should be explicitly noted in the individual test report. This synchronous transient immunity measurement method, as desc

22、ribed in this specification, uses short impulses with fast rise times of different amplitude, duration and polarity in a conductive mode to the IC. In this method, the applied impulse should be synchronized with the activity of the IC to make sure that controlled and reproducible conditions can be a

23、ssured. 2 Normative references The following referenced documents are indispensable for the application of this document. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document (including any amendments) applies. IEC 61967-4, Integ

24、rated circuits Measurement of electromagnetic emissions, 150 kHz to 1 GHz Part 4: Measurement of conducted emissions 1 /150 direct coupling method 3 Terms and definitions For the purposes of this document, the terms and definitions given in IEC 62215-1 (in preparation), as well as the following, app

25、ly. 3.1 auxiliary equipment AE equipment not under test that is nevertheless indispensable for setting up all the functions and assessing the correct performance (operation) of the equipment under test (EUT) during its exposure to the disturbance 3.2 coupling network electrical circuit for transferr

26、ing energy from one circuit to another with well-defined impedance and known transfer characteristics 3.3 device under test DUT device, equipment or system being evaluated DD IEC/TS 62215-2:2007DD IEC/TS 62215-2:2007 5 NOTE In this technical specification, it refers to a semiconductor device being t

27、ested. 3.4 electromagnetic compatibility EMC ability of an equipment or system to function satisfactorily in its electromagnetic environment without introducing intolerable electromagnetic disturbance to anything in that environment IEC 60050(161):1990, definition 161-01-07 3.5 electrical noise unwa

28、nted electrical signals, which produce undesirable effects in the circuits of the control system in which they occur IEEE std 100-1992-518-1982 3.6 immunity (to a disturbance) ability of a device, equipment or system to perform without degradation in the presence of an electromagnetic disturbance 3.

29、7 jitter (time related) short-term variations of the significant instants of a digital signal from their ideal positions in time 3.8 RF ambient totality of electromagnetic phenomena existing at a given location 3.9 transient pertaining to or designating a phenomenon or a quantity which varies betwee

30、n two consecutive steady states during a time interval which is short compared with the time-scale of interest IEC 60050(161):1990, definition 161-02-01 4 General 4.1 Introduction This immunity test method describes synchronous transient injection on digital and mixed-signal ICs. In this method an i

31、mpulse is injected into the Vss-, Vdd-pin(s) or I/Os successively on the IC subjected to the test. 4.2 Measurement philosophy This method is related to the 1 resistor method, see IEC 61967-4. In this method a 1 resistor is added in series with the Vdd, Vsspin(s) of the IC. It is assumed that the vol

32、tage drop across the 1 resistor in parallel with the DC by-pass inductance is very small. For injecting the impulse, a broadband coupling network is defined. The impulse injection is synchronized to a program loop signal generated by the IC. One cycle of this response signal is considered as one pro

33、gram loop. The aim of this measurement method is to insert a synchronous but delayed impulse into the IC, related to the program loop. The total time of one program loop period is calculated and then it is DD IEC/TS 62215-2:2007DD IEC/TS 62215-2:2007 6 divided into small time steps. At every delay s

34、tep, a single impulse per program loop is inserted into the IC and its response is measured. ClocksignalProgram loopsignalAdjustable delaypulse generatorImpulsesignalProgram loopdelayFigure 1 Synchronous transient injection immunity methodology waveforms Figure 1 shows the relevant signals occurring

35、 in this synchronous transient immunity test. The clock signal is used to run the digital IC and the program loop signal is used as a reference and response signal. A predetermined adjustable delay is used to shift the impulse delay time; delay, along the program loop.; delayis typically a fraction

36、( 0,1) of the rise time of the clock signal. The rising edge of the program loop signal, synchronized with the rising edge of the clock signal, is considered as a fixed reference point, see Figure 1, second line; program loop sync circuitry. Thereafter, the impulse is inserted and the edges of the r

37、esponse signals have to be observed. After every program loop, the delay step is increased and the injection moment of the impulse is shifted. In this way, the full scan can be completed through the program cycle to evaluate the impulse immunity. The test method will show sensitive time windows, i.e

38、. modes of operation at which the device is sensitive. The non-sensitive time windows can be skipped thereafter while repeating the measurements. NOTE This measurement methodology is different from to the stochastic i.e. random application of impulses. 4.3 Set-up concept In Figure 2, the block diagr

39、am of the test set-up for the synchronous impulse immunity test is given. A trigger signal, e.g. generated by the DUT, is used as an indication to start the measurement. This signal is also used to trigger the delay pulse generator to produce the programmable delay. The delayed pulse triggers the im

40、pulse generator that produces an impulse. This impulse is then inserted into the DUT through a suitable coupling network. Measurement equipment such as an oscilloscope or time domain analyser is used to measure the response of the DUT versus the delay of the impulse in the program loop. This measuri

41、ng equipment is also synchronized with the test signal to acquire the response data over a program loop. A computer interface is used to control the measurement test set-up and to acquire the response data from the test set-up. In general, the test set-up shall be in accordance with the specific tes

42、t procedure as described in the future IEC 62215-1. All the test relevant parameters shall be recorded as exactly as possible to ensure that the test results become reproducible. 4.4 Response signal The response signal is a signal generated by the IC under test (DUT). A clock signal may be externall

43、y provided. If the DUT is a microcontroller, then the response signal can be IEC 1712/07 DD IEC/TS 62215-2:2007DD IEC/TS 62215-2:2007 7 generated by a microcontroller by loading a small software program. If DUT is a logic device, then the output signal of the logic device is considered as the respon

44、se signal. The immunity can be quantified based on jitter occurring in the response signal (or any other errors) due to the impulse disturbances applied. DelaygeneratorImpulsegeneratorComputerMeasurementequipmentCouplingnetworkDUTClockgeneratorGPIBbusTriggersignalImpulsesignalProgram loop signalProg

45、ram loop sync circuitFigure 2 Test set-up diagram for synchronous transient injection immunity testing 4.5 Coupling networks 4.5.1 General The coupling network will always introduce a time delay for the applied impulse signal since a network presents a path (line) of a certain physical length for th

46、e signal. 4.5.2 Design of coupling networks For synchronous transient immunity testing, it is important that the coupling networks have a flat transfer characteristics over a broad frequency range. This flatness will help to couple the impulse to the DUT without disturbing its impulse characteristic

47、s and will maintain the normal operating conditions of the DUT. The coupling networks are designed in such a way that the impulses of different amplitude, duration, rise and fall time can be injected into the DUT ports. 4.5.3 Coupling network for the ground/ Vsspin(s) The principle used to couple th

48、e impulse into the ground/ Vsspin(s) is via a 1 resistor connected in series with a ground pin(s) of the IC and where the impulse signal is applied in series equivalently. Figure 3 shows an example of a coupling network. Two 4:1 transmission line (Guanella) transformers are used. A resistor network

49、follows these two transformers together with an RF choke. When the two TL (transmission line) transformers having impedance ratio 4:1 are connected in series, it results in an impedance step down from 50 to about 3 . The resistor network of 3 is connected as an RF load. To minimize the DC voltage drop across the 1 resistor, an RF choke of 10 H is connected in parallel. This inductor acts as a DC short-circuit and represents high impedance for the impulse sig