IEEE 1149 7-2009 en Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture (IEEE Computer Society)《缩减管脚和增强功能试验存取端口和边界扫描架构》.pdf

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1、IEEE Std 1149.7-2009IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture IEEE Computer Society Sponsored by the Test Technology Standards Committee IEEE 3 Park Avenue New York, NY 10016-5997, USA 10 February 2010 1149.7 TMIEEE Std 1149.7 TM -2009 I

2、EEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture Sponsor Test Technology Standards Committee of the IEEE Computer Society Approved 9 December 2009 IEEE-SA Standards Board Abstract: This specification describes circuitry that may be added to an i

3、ntegrated circuit to provide access to on-chip Test Access Ports (TAPs) specified by IEEE Std 1149.1 TM -2001. The circuitry uses IEEE 1149.1-2001 as its foundation, providing complete backward compatibility, while aggressively adding features to support test and applications debug. It defines six c

4、lasses of 1149.7 Test Access Ports (TAP.7s), T0T5, with each class providing incremental capability, building on that of the lower level classes. Class T0 provides the behavior specified by 1149.1 from startup when there are multiple on-chip TAPs. Class T1 adds common debug functions and features to

5、 minimize power consumption. Class T2 adds operating modes that maximize scan performance. It also provides an optional hot-connection capability to prevent system corruption when a connection is made to a powered system. Class T3 supports operation in either a four- wire Series or Star Scan Topolog

6、y. Class T4 provides for communication with either a two-pin or four-pin interface. The two-pin operation serializes 1149.1 transactions and provides for higher Test Clock rates. Class T5 adds the ability to perform data transfers concurrent with scan, supports utilization of functions other than sc

7、an, and provides control of TAP.7 pins to custom debug technologies in a manner that ensures current and future interoperability. Keywords: 1149.1, 1149.7, 2-pin, 2-wire, 4-pin, 4-wire, Advanced Protocol, Advanced Protocol Unit, APU, Background Data Transfer, background data transport, BDX, boundary

8、 scan, BSDL, BSDL.1, BSDL.7, BYPASS, Capture-IR, CDX, Chip-Level TAP Controller, CID, Class T0, Class T1, Class T2, Class T3, Class T4, Class T5, CLTAPC, compact JTAG, compliant behavior, compliant operation, control level, controller address, Controller ID, Controller Identification Number, CP, Cus

9、tom Data Transfer, custom data transport, Data Register, debug interface, debug logic, debug and test interface, DOT1, DOT7, DTI, DTS, DTT, Debug Test System, debug test target, Escape, EOT, EPU, extended operation, Extended Protocol, EXTEST, HSDL, HSDL.7, IDCODE, Instruction Register, JScan, JScan0

10、, JScan1, JScan2, JScan3, JTAG, MScan, MTCP, Multi-TAP Control Path, narrow Star Scan Topology, nTRST, nTRST_PD, optimized scan, OScan, OScan0, OScan1, OScan2, OScan3, OScan4, OScan5, OScan6, OScan7, 1149.1, 1149.7, Pause-DR, Pause-IR, PC0, PC1, RSU, Reset and selection unit, RTI, Run-Test/Idle, sca

11、n, scan DR, scan format, scan IR, Scan Packet, scan path, scan performance, scan protocol, scan topology, series, Series Branch, Series Scan, Series Scan Topology, Series-Equivalent Scan, Series Topology, Shift-DR, Shift-IR, SiP, Star Scan, Star Scan Topology, Star Topology, Star-2, Star-2 Branch, S

12、tar-2 Scan, Star-2, Scan Topology, Star-4, Star-4 Branch, Star-4 Scan, Star-4 Scan Topology, SP, SScan, SScan0, SScan1, SScan2, SScan3, stall, SSD, Scan Selection Directive, Standard Protocol, star scan, STL, System Test Logic, TAP, TAP controller, TAP controller address, TAP selection, TAP.1, TAP.7

13、, TAP.7, TAPC, TCA, TCKC, TDI, TDIC, TDOC, TDOE, Test Access Port, test and debug, Test-Logic-Reset, TLR, TMSC, Transport Packet, T0, T0 TAP.7, T1, T1 TAP.7, T2, T2 TAP.7, T3, T3 TAP.7, T4, T4 TAP.7, T4(N), T4(N) TAP.7, T4(W), T4(W) TAP.7, T5, T5 TAP.7, T5(N), T5(N) TAP.7, T5(W), T5(W) TAP.7, TP, Up

14、date-DR, Update-IR, ZBS, zero bit scan The Institute of Electrical and Electronics Engineers, Inc. 3 Park Avenue, New York, NY 10016-5997, USA Copyright 2010 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Published 10 February 2010. Printed in the United States o

15、f America. IEEE is a registered trademark in the U.S. Patent +1 978 750 8400. Permission to photocopy portions of any individual standard for educational classroom use can also be obtained through the Copyright Clearance Center. iv Copyright 2010 IEEE. All rights reserved. Introduction This introduc

16、tion is not part of IEEE Std 1149.7-2009, IEEE Standard for Reduced-Pin and Enhanced- Functionality Test Access Port and Boundary-Scan Architecture. This standard defines a debug and Test Access Port that provides both compatibility with IEEE Std 1149.1 TM -2001 aand operation with as few as two pin

17、s. It complements IEEE Std 1149.1-2001 and is not intended to replace it. The facilities defined by the standard seek to provide a cost-effective debug and test interface solution supporting the debug and test of applications. The standard supports the needs for application debug of products with co

18、mplex digital circuitry, applications software, and one or more central processing units (CPUs). The interface also provides a means to instrument these applications concurrent with scan transactions associated with the underlying IEEE 1149.1 foundation. The process of developing this standard began

19、 in 2004 when the Mobile Industry Processor Interface (MIPI) Alliance Test and Debug Working Group was formed. During 2004, a standard that addressed the needs of both test and debug was described and requirements were gathered. The emphasis was on creating an interface that allowed standardization

20、of access to debug and test capabilities on-chip while at the same time addressing the needs of applications developers sharing an integrated circuits Test Access Port with test uses. This interface also targeted making chips exhibit the behavior that is specified by IEEE Std 1149.1-2001 when multip

21、le Test Access Ports are deployed on a single chip. It was thought that applications development tools vendors would be a big beneficiary of this interface as common connectors providing access to the debug and test interface would be recommended. It was felt that all of this would best be accomplis

22、hed with an interface that was compatible with chip intellectual property already utilizing IEEE Std 1149.1-2001. Once the requirements gathering process was completed in 2004, the Test and Debug Working Group turned its attention to proposals for addressing the above requirements. Both competing an

23、d complementary proposals were submitted. The proposals were debated, and one was selected as a basis to move forward in April of 2005. A preliminary specification replaced the proposal and was reviewed inside the MIPI Test and Debug Working Group and by the NEXUS standards body in late 2005. Since

24、both bodies felt the applicability of the specification was well beyond their own objectives, they both recommended using the on-chip portions of those specifications as the basis for an IEEE standard in a joint meeting in December of 2005. Multiple drafts of the specification were completed and rev

25、iewed from 2005 until the standards approval, with the capability provided by the standard expanded along the way. Revisions in the presentation and number of capabilities took place along the way to the standards unanimous approval in 2009. Notice to users Laws and regulations Users of these docume

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