JEDEC JESD99C-2012 Terms Definitions and Letter Symbols for Microelectronic Devices.pdf

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1、JEDEC STANDARD Terms, Definitions, and Letter Symbols for Microelectronic Devices JESD99C (Revision of JESD99B, May 2012 DECEMBER 2012 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Bo

2、ard of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products

3、, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their ado

4、ption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications rep

5、resents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to

6、be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and

7、 Documents for alternative contact information. Published by JEDEC Solid State Technology Association 2012 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file th

8、e individual agrees not to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid State Technol

9、ogy Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 99C -i- TERMS, DEFINITIONS, AND LETTER SYMBOLS FOR MICROELECTRONIC DEVICES CONTENTS PageForeword iiiSECTION 1: PHYSICAL TERMS

10、1.1 Definitions of physical terms applicable to integrated circuits in general 1-11.2 Definitions of physical terms applicable to gate arrays or cell-based integrated circuits 1-23SECTION 2: PARAMETRIC AND DESCRIPTIVE TERMS 2.1 General guidelines for letter symbols and abbreviations 2-12.1.1 Definit

11、ions of letter symbols and abbreviations 2-12.1.2 Criteria and conventions for letter symbols and abbreviations 2-12.2 Terms and definitions applicable to all integrated circuits 2-92.2.1 General concepts 2-92.2.2 Boundary concepts 2-102.2.3 Stability characteristics 2-102.2.4 Voltage, current, and

12、power 2-112.2.5 Junction temperature, thermal resistance, and virtual junction 2-112.2.6 Types of outputs 2-122.3 Terms and definitions applicable to digital integrated circuits 2-192.3.1 General digital concepts 2-192.3.2 Voltage 2-202.3.3 Current 2-212.3.4 Resistance 2-222.3.5 Time intervals and c

13、lock frequency 2-222.4 Terms and definitions applicable to linear (analog) integrated circuits 2-282.4.1 General linear concepts 2-282.4.2 Amplification and gain 2-282.4.3 Frequency, time, and transient response 2-292.4.4 Input voltage 2-312.4.5 Output voltage 2-312.4.6 Current 2-322.4.7 Resistance

14、and impedance 2-322.4.8 Rejection ratio and sensitivity 2-332.4.9 Temperature coefficient 2-332.4.10 Noise and distortion 2-342.5 Terms and definitions applicable to interface integrated circuits 2-352.5.1 General interface concepts and types 2-352.5.2 Analog-to-digital converters and digital-to-ana

15、log converters 2-362.6 Terms and definitions applicable to voltage regulator integrated circuits 2-582.6.1 General voltage regulator concepts 2-582.6.2 Regulator, drift, and temperature coefficient 2-592.6.3 Voltage level 2-59JEDEC Standard No. 99C -ii- TERMS, DEFINITIONS, AND LETTER SYMBOLS FOR MIC

16、ROELECTRONIC DEVICES CONTENTS (continued) Page2.6.4 Current 2-602.6.5 Noise 2-602.6.6 Impedance 2-602.6.7 Time 2-602.7 Terms and definitions applicable to charge-transfer devices 2-612.7.1 Types of charge-transfer devices 2-612.7.2 General concepts of charge-transfer device 2-622.7.3 Efficiencies, i

17、nefficiencies, and loss 2-642.7.4 Input signals and dynamic range 2-652.7.5 Dark current (charge-coupled image sensors) 2-662.7.6 Transfer time 2-66Annex A (informative): Differences between JESD99C and JESD99-A A-1Index Index-1JEDEC Standard No. 99C -iii- Foreword This standard will prove to be a u

18、seful guide for users, manufacturers, educators, technical writers, and others interested in the characterization, nomenclature, and classification of microelectronic devices. It lists and defines the most common physical and electrical terms applicable to these devices and shows the industry-standa

19、rd symbols and abbreviations that have been established for such terms. Where applicable, reference is made to standardization documents of the following organizations: American National Standards Institute, Inc. (ANSI) Electronic Industries Association (EIA and JEDEC) Institute of Electrical and El

20、ectronics Engineers (IEEE) International Electrotechnical Commission (IEC) National Institute of Standards and Technology (NIST) The material contained in this standard was formulated under the cognizance of EIA/JEDEC Committee JC-10 on Terms, Definitions, and Symbols and approved by the JEDEC Board

21、 of Directors. The text of this standard is based on JESD99B dated May 2007, which it replaces, and JEDEC Board ballots JCB-09-88 and JCB-11-56.- Annex A briefly shows entries that have been changed. JEDEC Standard No. 99C -iv- JEDEC Standard No. 99C Page 1-1 SECTION 1: PHYSICAL TERMS 1.1 Definition

22、s of physical terms applicable to integrated circuits in general ac test: The process of verifying the specified timing of a device. NOTE Testing of propagation delays, minimum setup and hold times, minimum pulse durations, etc., can be performed by using test vectors applied at specified operating

23、frequency of the device. Propagation delays of critical logic paths for system operation can be measured individually. (Ref. JESD12-1B.) active device: A device in which at least one circuit element is an active circuit element. application-specific integrated circuit (ASIC): An integrated circuit d

24、eveloped and produced for a specific application or function and for a single customer. NOTE ASICs generally use standard cell or gate array design methodology. application-specific standard product (ASSP): An integrated circuit developed and produced for a specific application or function but made

25、available for multiple customers. artwork: The original, accurately scaled, oversize drawings and plastic overlays of the microcircuit topological layout that are used to produce the master mask plates. NOTE Artwork has largely been supplanted by computer-produced drawings and masks. assembly, micro

26、electronic: An assembly of unpackaged (uncased) microcircuits and/or packaged microcircuits, which may also include discrete devices, so constructed on a packaging interconnect structure that for the purpose of specification, testing, commerce, and maintenance, the package is considered to be an ind

27、ivisible component. (Ref. JESD30-B.) NOTE 1 The passive and/or active discrete and microelectronic devices may be mounted on either one or two sides of the packaging interconnect structure, and the external terminals usually exit from one side of the assembly. NOTE 2 Many package sizes, shapes, and

28、external terminal forms are possible. asynchronous circuit: A circuit whose changes of state are not controlled by a single clock. (Ref. JESD12-1B.) autodoping: The introduction of impurities from the substrate into the epitaxial layer during the process of epitaxy. base (of a package): The part of

29、a package that includes the surface on which a chip is intended to be mounted. beam lead: A thick-film lead formed on and attached to the chip interconnection pattern and projecting cantilevered beyond the chip periphery for attachment to a substrate. JEDEC Standard No. 99C Page 1-2 1.1 Definitions

30、of physical terms applicable to integrated circuits in general (contd) bipolar-and-CMOS (BiCMOS) technology: A technology for combining bipolar transistors and silicon-gate complementary metal-oxide-semiconductor (CMOS) field-effect devices in a single-chip integrated circuit. bipolar-and-CMOS-and-D

31、MOS (BCD) technology: A technology for combining bipolar transistors, silicon-gate complementary metal-oxide-semiconductor (CMOS) field-effect devices, and double-diffused metal-oxide-semiconductor (DMOS) field-effect transistors in a single-chip integrated circuit. bipolar-and-FET (BiFET) technolog

32、y: A technology for combining bipolar transistors and junction-gate field-effect transistors (JFET) in a single-chip integrated circuit. bipolar-and-MOS (BiMOS) technology: A technology for combining bipolar transistors and metal-gate metal-oxide-semiconductor (MOS) or metal-gate complementary metal

33、-oxide-semiconductor (CMOS) field-effect devices in a single-chip integrated circuit. bipolar technology: A technology for producing devices in which electrical conduction depends on the flow of both majority and minority carriers. body (of a semiconductor device): The semiconductor portion of a dev

34、ice limited by the physical extent of the crystalline or amorphous semiconductor material and including any associated oxide layers and metallization. bond, ball: A thermocompression bond in which the attachment wire has been fed through a capillary tube and its exposed end melted into a ball that h

35、as been attached under pressure to the bonding pad. bond, chip: The attachment of the circuit chip to a hybrid or package substrate. NOTE The attachment serves as a mechanical support, a thermal path, and sometimes an electrical contact. bond, die: Synonym for “semiconductor chip bond”. bond, face:

36、A bond directly between a chip bonding pad and a mounting substrate for the purpose of making electrical contact. bond, stitch: A thermocompression bond in which a capillary tube is used for both feeding the wire and forming the bond. bond, thermocompression: A bond in which two members are joined t

37、hrough the combined application of heat and pressure. bond, ultrasonic: A bond in which two members are joined through the combined application of pressure and an ultrasonic oscillatory lateral motion. bond, wedge: A thermocompression bond in which a wedge-shaped tool is used to apply pressure to th

38、e wire being attached. JEDEC Standard No. 99C Page 1-3 1.1 Definitions of physical terms applicable to integrated circuits in general (contd) bond, wire: The attachment between a bonding wire and a chip bonding pad or package terminal. bonding wire: A wire that is bonded to a chip bonding pad in ord

39、er to connect the chip to any other point within the device package. boundary scan: A design methodology in which the I/O buffers of a circuit or functional block are observed and controlled by scan cells. (Ref. JESD12-1B.) NOTE The boundary scan standard was developed by the Joint Test Action Group

40、 (JTAG) and is embodied in ANSI/IEEE Std 1149-1. case: Synonym for “package”. channel: A region of semiconductor material in which current flow is influenced by a transverse electrical field. NOTE 1 A channel may physically be an inversion layer, a diffused layer, or bulk material. NOTE 2 The type o

41、f channel, i.e., p-channel or n-channel, is determined by the type of majority carrier during conduction. charge pump: (1) A dc-to-dc converter in which a capacitor is charged from a voltage source and then electrically reconnected in series with that source to make available a voltage greater than

42、that of the source. NOTE This type of dc-to-dc converter is sometimes called a voltage doubler or, when several stages are cascaded, a voltage multiplier. (2) A dc-to-dc converter in which a capacitor is charged from a voltage source and then electrically reconnected to make available a voltage whos

43、e polarity is opposite to that of the source. chip: A separated part of a wafer (or, in some cases, a whole wafer) intended to perform a function or functions in a device. chip, beam-lead: A chip employing electrical terminations in the form of tabs extending beyond the edge of the chip for direct b

44、onding to a mounting substrate. chip carrier: A package whose chip cavity or mounting area occupies a major fraction of the package area and whose terminals consist of metal pad surfaces (on leadless versions) or leads formed around the sides and under the package or out from the package (on leaded

45、versions). NOTE The term “chip carrier” has been replaced by “quad flatpack” (for terminals on three or four sides) and “small-outline package” (for terminals on one or two sides). JEDEC Standard No. 99C Page 1-4 1.1 Definitions of physical terms applicable to integrated circuits in general (contd)

46、chip, face-down: A chip whose electrical terminations are on the side that is intended to be attached to the mounting substrate. chip, face-up: A chip whose electrical terminations are on the side opposite the one that is intended to be attached to the mounting substrate. chip, flip: A chip with bum

47、p contacts spaced around the device and intended for face-down mounting. circuit element: Any constituent part of a circuit that contributes directly to its operation and performs a definable function. NOTE 1 Examples include transistors, resistors, capacitors, inductors, and interconnections. NOTE

48、2 The definition in JESD12-1B excludes interconnections. circuit element, active: A circuit element that contributes qualities to a circuit function other than those contributed by a passive circuit element, e.g., rectification, switching, gain, or conversion of energy from one form to another. NOTE

49、 1 Examples include diodes, transistors, active integrated circuits, and light-sensing or light-emitting devices. NOTE 2 Active physical circuit elements may also be used to act as passive physical circuit elements, e.g., to provide resistance and/or capacitance to a circuit function. circuit element, parasitic: A circuit element that is an unavoidable adjunct of one or more other circuit elements. circuit element, passive: A circuit element primarily contributing resistance, capacitance, inductance, ohmic interconnection, or a combination of these to a circuit function. NOTE Examples