JEDEC JESD92-2003 Procedure for Characterizing Time- Dependent Dielectric Breakdown of Ultra-Thin Gate Dielectrics《超薄绝缘体口有时间决定的介质击穿的辨别规程》.pdf

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1、JEDEC STANDARD Procedure for Characterizing Time-Dependent Dielectric Breakdown of Ultra-Thin Gate Dielectrics JESD92 AUGUST 2003 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board o

2、f Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and

3、 assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption

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5、ts a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI/EIA standard. No claims to b

6、e in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or www.jedec.org Publis

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8、 PRICE: Please refer to the current Catalog of JEDEC Engineering Standards and Publications online at http:/www.jedec.org/Catalog/catalog.cfm Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. Or

9、ganizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No.92 -i- PROCEDURE FOR C

10、HARACTERIZING TIME-DEPENDENT DIELECTRIC BREAKDOWN OF ULTRA-THIN GATE DIELECTRICS CONTENTS Page Foreword. i 1 Scope 1 2 Overview . 1 3 Terms and definitions 2 4 Constant voltage test procedure 4.1 Test configuration 4 4.2 Pre-characterization test.5 4.3 Pre-CVS oxide current test 6 4.4 Constant volta

11、ge stress test 7 4.5 Post-CVS oxide current test.12 4.6 Data recording12 4.7 Oxide failure categories .13 5 Bibliography . 14 Annex A: (informative) Supplemental data analysis A.1 Test structures.16 A.2 Determining Oxide Electric Field20 A.3 Extrapolation models .21 A.4 Determining Failure Rates .23

12、 TABLES 1 Oxide failure catagories.20 A.1 Reliability characteristics for weibull distributions .33 FIGURES 1 Stress gate current vs. time.16 2 Block diagram and timing diagram.18 JEDEC Standard No.92 -ii- PROCEDURE FOR CHARACTERIZING TIME-DEPENDENT DIELECTRIC BREAKDOWN OF ULTRA-THIN GATE DIELECTRIC

13、S Foreword This document is intended for use MOS integrated circuit manufacturing. It describes a test procedure for estimating the acceleration parameters of “wear-out” or Time-Dependent-Dielectric Breakdown (TDDB) of ultra-thin (tox10 X average value Iuse determined from the pre-characterization t

14、est, record as initial failure. 6) Optional: If ImeasIleak, record as yield failure. JEDEC Standard No. 92 Page 7 4 Constant voltage test procedure (contd) 4.4 Constant voltage stress test Devices that pass the pre-CVS test are then subject to the constant voltage test. In order that the compliance

15、circuit in the test equipment does not interfere with the determination of breakdown it is recommended that the compliance of the test system (Icomp) be at least 10X greater than Istress 4. 1) Apply or ramp the voltage to the stress voltage (Vstress) ensuring that voltage overshoots do not exceed 1%

16、 of Vstress. The voltage ramp time should be less that 1% of the anticipated time-to-fail (tbd). The minimum value is 100 ms. After the voltage ramp, the voltage is held at Vstress and the current is periodically monitored and logged to a data file. The current can be monitored at short time interva

17、ls (tmeas); however, the current should be recorded in the data file at time intervals (trecord). The record time interval should be less than 1% of the anticipated time-to-fail (tbd). For practical considerations trecordcan be evenly spaced log time intervals. The logged data can be used to validat

18、e the actual breakdown event. 2) The device is considered to have failed when one of the following breakdown conditions has been detected: a) Increase in measured oxide current For thicker oxides (tox 5 nm) or for small area test structures the oxide often fails by a sudden increase (10X) in measure

19、d oxide stress current. Imeas 10 X Iprevious. If this condition is met the test is terminated and the post-test is performed. Note that value of 10X increase is a recommended value. This value could range between 2-10X for actual hard breakdown events depending on capacitor area, thickness, structur

20、e, or process. The breakdown time and Imeasshould be recorded. The breakdown is classified as “Hard”. JEDEC Standard No. 92 Page 8 4 Constant voltage test procedure (contd) 4.4 Constant voltage stress test (contd) b) Increase in current noise 5 At a soft-breakdown oxide event the measurement noise i

21、ncreases. This increase in noise can be detected by analyzing the current measurement data using variance techniques. This test description assumes that the test system noise has already been determined as described in the pre-characterization test (See 4.2). In this test six consecutive current val

22、ues of Imeas(i) to Imeas(i+5) are recorded and the current noise (Imeas)2is calculated from these values as: NOTE The final value of (Imeas)2is essentially the estimator of the sample variance of five Imeasvalues. The current noise is continually calculated by adding a new current value and deleting

23、 the first value in the six-point set (i.e., a sliding sample set: Imeas(i+1) to Imeas(i+5). If the current noise increases by 500X over the baseline value determined in 3.2 for at least five additional calculations, then the device is defined as failed. The additional calculations performed past th

24、e detection of breakdown assures that the noise increase is sustained and not a result of a random fluctuation or a transient noise increase. The test is then terminated and the post-test performed. Note that value of 500X increase is a recommended value. This value could range between 200X and 500X

25、 for actual soft breakdown events depending on capacitor area, thickness, structure, or process. It may be desirable to compensate for slowing increasing values of Imeasduring the stress due to trapping or stress-induced leakage current. In this case, the value of (Imeas)2can be calculated from the

26、variance of five values of the difference between the Imeas(i+1) - Imeas(i) data points in the six point sample as follows: (Imeas)22=i=5i=1Imeas(i)2-i=5i=1Imeas(i) 54(Imeas)2=i=5i=14Imeas(i+1) Imeas(i)2-i=5i=125Imeas(i+1) Imeas(i)JEDEC Standard No. 92 Page 9 4 Constant voltage test procedure (contd

27、) 4.4 Constant voltage stress test (contd) Figure 1 illustrates a typical example of implementing the variance method for detecting breakdown. The example is for a 2.0 nm thick SiO2sample with an area of 4 x 10-6cm2. Note that more than a four-order-of-magnitude increase in the current noise is obse

28、rved at the onset of dielectric breakdown. Figure 1 Stress gate current vs. time and gate current noise vs. time for a 2.0 nm thick SiO2film with an area of 4 x 10-6cm2. The onset of breakdown is detected by a 500X increase in the current noise. Ultra-thin oxides have been observed to exhibit rapid

29、current transients and random telegraph signals (RTS) before breakdown. Care must be taken to avoid detecting breakdown under these conditions. A technique described in 6 has been shown to reduce sensitivity to RTS and other transient behavior. The breakdown time and pre/post breakdown noise level s

30、hould be recorded. The breakdown is classified as “Soft”. Time (s)0 500 1000 1500 2000gatecurrent (A)var(I)1e-211e-201e-191e-181e-171e-161e-151e-141e-131e-121e-111e-101e-91e-81e-71e-61e-51e-41e-31e-2gate currentvariance of delta Ibaselinesample size = 5tox= 2.0 nmArea=4 x 10-6cm2500X increaseJEDEC S

31、tandard No. 92 Page 10 4 Constant voltage test procedure (contd) 4.4 Constant voltage stress test (contd) c) Increase in low voltage stress-induced leakage current (SILC) This method monitors the increase of SILC as a function of stress time to determine when soft-breakdown has occurred. In this tec

32、hnique at periodic time intervals (tint) the voltage stress is interrupted and device current (Imeas) measured at low gate voltage (VSILC). The value of VSILCis typically 1 V to 2 V. After stress interruption and before the Imeasmeasurement a wait time (twait) should occur to allow any transients to

33、 diminish which may occur in some test systems. The tint value should be F x Imeas(VG, tint), then the device is defined as failed. The test is terminated and the post-test is conducted. Typical values of F are between 2 to 5. The value depends on tox, Aoxide, and VSILC. Figure 2 shows block and tim

34、ing diagrams describing the stress interruption technique. It has been shown that periodic stress interruption does not affect the lifetime distributions for a variety of stress conditions 7,8. The breakdown time and pre/post breakdown ISILClevel should be recorded. The breakdown is classified as “S

35、oft”. JEDEC Standard No. 92 Page 11 4 Constant voltage test procedure (contd) 4.4 Constant voltage stress test (contd) Figure 2 Block diagram and timing diagram showing the implementation of the stress interruption technique for monitoring the change in SILC (tintmust be t int No Measure I SILC at V

36、 SILC I SILC (t int+1 ) 5XI SILC (t int ) Wait t wait Yes No Yes Record Breakdown Time Time V stressV SILCt waitt intStress phase I SILCMeasurement Post - CVS Oxide Current Test Pre - CVS Oxide Current Test Force VSILC JEDEC Standard No. 92 Page 12 4 Constant voltage test procedure (contd) 4.5 Post-

37、CVS oxide current test Following breakdown detection as defined in 4.4 or if the test is user terminated, a post-test similar to the pre-test should be conducted as follows: 1) Force Vuse2) Measure Imeas3) If Imeas 10 X Iuse, record as Catastrophic Failure. (Note that this condition is expected be f

38、alse in all cases where soft breakdown occurred and was detected by the noise or SILC detection methods discussed in 4.4.) 4.6 Data recording For all catastrophic failures (desired failure category, see Table 1) record the following information as outlined below. tbd- oxide time-to-breakdown. qbd- t

39、he accumulated oxide breakdown charge density. Failure category the oxide failure mode as defined in 4.7. In addition it is recommended that the following parameters be recorded: Ibd(Vstress) - the oxide breakdown current measured at the stress voltage. (Optional) Ibd(Vlow) - the oxide breakdown cur

40、rent measured at a defined low voltage. JEDEC Standard No. 92 Page 13 4 Constant voltage test procedure (contd) 4.7 Oxide failure categories Because of the complexity of the oxide test procedure, five possible oxide failure types can occur. These failure types are listed in Table 1 and discussed in

41、this section: Table 1 Oxide failure categories Stress failure type Pre-test CVS test Post-test Recorded parameters Type I Fail N/A N/A Failure type I Type II.x Pass Fail Fail Failure type II, tbd, Ibd( Vstress), (Imeas)2or ISILCType III Pass Pass Fail Failure type III Type IV.x Pass Fail Pass Failur

42、e type IV, tbd, Ibd( Vstress), (Imeas)2or ISILCType V Pass Pass Pass Failure type V NOTE The “x” indicates what breakdown criterion was used to detect breakdown: x = 1 (compliance or Imeas 10 X Iprevious), x = 2 (current noise), x = 3 (change in ISILC).Pass in the pre-test indicates that the initial

43、 oxide current did not exceed the failure criteria, i.e., the oxide was not “shorted”. Pass in the post-test also indicates that the oxide current did not exceed the failure criteria, i.e., it was not “shorted”. Pass in the CVS test indicates that oxide breakdown was not detected with one of the fai

44、lure criteria specified in 4.4.1. JEDEC Standard No. 92 Page 14 5 Bibliography 1. Degraeve, R., et al., Reliability: a possible showstopper for oxide thickness scaling, Semicond. Sci. Tech., Vol. 15, 2000, p. 425. 2. Monsieur, F., et al., “Determination of Dielectric Breakdown Weibull Distribution P

45、arameters Confidence Bounds for Accurate Ultra-thin Oxide Reliability Predictions,” Proc. of ESREF, 2001, p.1. 3. Synder, E.S., and J. S. Suehle, “Detecting Breakdown in Ultra-Thin Dielectrics Using a Fast Voltage Ramp,” IEEE Integrated Reliability Workshop Final Report, Lake Tahoe, CA, 1999, pp. 11

46、8-123. 4. Brisbin, D., et al., Microelectronics Reliability, 2002, Vol. 42, p. 35. 5. Alers, G.B., et al., “J-Ramp on Sub-3 nm Dielectrics: Noise as a Breakdown Criterion,” Proc. International Reliability Physics Symposium, Vol. 37, 1999, pp. 410-413. 6. Roussel, P., et al., Proc. International Reli

47、ability Physics Symposium, Vol. 39, 2001, pp. 386-391. 7. Pompl, T., et al., Proc. International Reliability Physics Symposium, Vol. 37, 1999, pp. 82-87. 8. Wang, B., et al., IEEE Integrated Reliability Workshop Final Report, Lake Tahoe, CA, 2000, pp. 74-79. 9. Richter, C.A., et al., “A Comparison o

48、f Quantum-Mechanical Capacitance-Voltage Simulators,” IEEE Elec. Dev. Lett., Vol. 22, 2001, pp. 35-37. 10. McPherson, J., and D.A. Baglee, “Acceleration Factors for Thin Gate Oxide Stressing,” Proc. International Reliability Physics Symposium, Vol. 23, 1985, pp. 1-5. 11. McPherson, J.W., and R.B. Kh

49、amankar, Molecular Model for Intrinsic Time-Dependent Dielectric Breakdown in SiO2Dielectrics and the Reliability Implications for Hyper Thin Gate Oxide, Semicond. Sci. Technol, Vol. 15, 2000, pp. 462-470. 12. Hu, C., and Q. Lu, “A Unified Gate Oxide Reliability Model,” Proc. International Reliability Physics Symposium, Vol. 37, 1999, pp. 47-51. 13. Schuegraf, K.F., and C. Hu, “Metal-Oxide-Semiconductor Field-Effect-Transistor Structures Substr