JEDEC JESD8C 01-2007 Interface Standard for Nominal 3 V 3 3 V Supply Digital Integrated Circuits (Minor Revision of JESD8C June 2006).pdf

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1、JEDEC STANDARD Interface Standard for Nominal 3 V/3.3 V Supply Digital Integrated Circuits JESD8C.01 (Minor Revision of JESD8C, June 2006) SEPTEMBER 2007 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved t

2、hrough the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and impr

3、ovement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to wheth

4、er or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards a

5、nd publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI stan

6、dard. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or

7、www.jedec.org Published by JEDEC Solid State Technology Association 2007 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the

8、 resulting material. PRICE: Please refer to the current Catalog of JEDEC Engineering Standards and Publications online at http:/www.jedec.org/Catalog/catalog.cfm Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced wi

9、thout permission. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 8

10、C.01 -i- INTERFACE STANDARD FOR NOMINAL 3 V/3.3 V SUPPLY DIGITAL INTEGRATED CIRCUITS CONTENTS Contents Page 1 Scope 1 2 Standard Specifications 1 2.1 Absolute Maximum Ratings 1 2.2 Recommended Operating Conditions 2 2.3 DC Electrical Characteristics 2 2.4 Optional DC electrical characteristics for S

11、chmitt trigger operation 3 3 Test conditions for optional Schmitt trigger operation 4 4 Background 5 4.1 Requirements for Scaling 5 4.2 LVTTL Compatibility 5 4.3 LVCMOS Compatibility 6 4.4 Meeting Standard 8C Requirements 6 4.5 Exceeding Standard 8C Requirements 6 Annex A Differences between JESD8C.

12、01 and JESD8C 7 Annex A.1 Differences between JESD8C and JESD8B 7 Tables 1 Recommended operating conditions 2 2 LVTTL & LVCMOS input specifications 2 3 LVTTL output specifications 2 4 LVCMOS output specifications 3 5 Input/Output Specification 3 6 Input/Output Specification 4 Figures 1 DC characteri

13、stic measurement circuit of Schmitt trigger input 4 JEDEC Standard No. 8C.01 -ii- JEDEC Standard No. 8C.01 Page 1 INTERFACE STANDARD FOR NOMINAL 3 V/3.3 V SUPPLY DIGITAL INTEGRATED CIRCUITS (From JEDEC Board Ballot JCB-98-120, and JCB-05-76, formulated under the cognizance of the JC-16 Committee on

14、Interface Technology.) 1 Scope This standard (a replacement of JEDEC Standards 8, 8-1, 8-1A, and 8B) defines dc interface parameters for a family of digital circuits operating from a power supply of nominal 3 V/3.3 V and driving/driven by parts of the same family. Clause 2 describes normal DC electr

15、ical characteristics and clause 2.4 (added by revision C) describes the optional characteristics for Schmitt trigger operation. The specifications in this standard represent a minimum set, or base line set, of interface specifications for LVTTL compatible and LVCMOS compatible circuits. Conversion t

16、o this standard will not occur at any specific time. Instead, manufacturers forced to reduce operating voltages for any of the reasons summarized in clause 4 should convert to this base line standard as a basis for their designs to ensure compatibility in a nominal 3 V/3.3 V power supply environment

17、. The purpose is to develop a standard of specifications to provide for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design. 2 Standard specifications All voltages listed are referenced to ground (0 V) except where noted. 2.1 Absolute maximum ra

18、tings (Notes 1 & 2) Supply Voltage: VDD-0.5 V to 4.6 V DC input Voltage: VI-0.5 V to VDD+ 0.5 V ( 4.6 V max.) DC Output Voltage: VO.-0.5 V to VDD+ 0.5 V ( 4.6 V max.) DC Input Current: IIat VIVDD20 mA DC Output Current IOat VOVDD.20 mA NOTE 1 Absolute Maximum Ratings are those values beyond which da

19、mage to the device may occur. Functional operation under these conditions or at any other condition beyond those indicated in the operational sections of this standard is not implied. NOTE 2 IIis for any single input and IOis for any single output. JEDEC Standard No. 8C.01 Page 2 2 Standard specific

20、ations (contd) 2.2 Recommended operating conditions Table 1 Recommended operating conditions Power supply range Symbol Narrow Range Normal Range Extended RangeNominal supply voltage VDD3.3 V 3.3 V 3.0 V Power supply voltage VDD3.15 V to 3.45 V 3.0 V to 3.6 V 2.7 V to 3.6 V Operating temperature TASe

21、e Note See Note See Note NOTE As specified by manufacturer to be Commercial, Industrial and/or Military grade. 2.3 DC electrical characteristics All specifications in the following tables apply across the operating temperature range. Table 2 LVTTL & LVCMOS input specifications Symbol Parameter Test

22、condition (note 1) MIN MAX Units VIHInput High Voltage 2 VDD+0.3 V VILInput Low Voltage VOUT= VOH (min)or VOUT VOL (max)-0.3 0.8 V IINInput Current VIN= 0 V or VIN= VDD(Note 2) 5 A 3.0 V nominal supply: VDD (min)= 2.7 V and VDD (max)= 3.6 V 3.3 V nominal supply: VDD (min)= 3.0 V and VDD (max)= 3.6 V

23、 3.3 V nominal supply: VDD (min)= 3.15 V and VDD (max)= 3.45 V NOTE 1 For conditions shown as min or max, use the appropriate value shown in Tables 3 and 4. NOTE 2 Excluding common Input/Output terminals. Table 3 LVTTL output specifications Symbol Parameter Test condition MIN MAX Units VOHOutput Hig

24、h Voltage VDD= min, IOH= -2 mA 2.4 V VOLOutput Low Voltage VDD= min, IOL= 2 mA 0.4 V 3.3 V nominal supply: VDD (min)= 3.0 V and VDD (max)= 3.6 V 3.3 V nominal supply: VDD (min)= 3.15 V and VDD (max)= 3.45 V JEDEC Standard No. 8C.01 Page 3 2 Standard specifications (contd) 2.3 DC electrical character

25、istics (contd) Table 4 LVCMOS output specifications Symbol Parameter Test condition MIN MAX Units VOHOutput High Voltage VDD= min, IOH= -100 A VDD - 0.2 V VOLOutput Low Voltage VDD= min, IOL= 100 A 0.2 V 3.0 V nominal supply: VDD (min)= 2.7 V and VDD (max)= 3.6 V 3.3 V nominal supply: VDD (min)= 3.0

26、 V and VDD (max)= 3.6 V 3.3 V nominal supply: VDD (min)= 3.15 V and VDD (max)= 3.45 V 2.4 Optional DC electrical characteristics for Schmitt trigger operation 2.4.1 Optional Schmitt trigger operation - Normal range Table 5 Input/Output Specification VDD (min)= 3.0 V and VDD (max)= 3.6 V Symbol Param

27、eter Test Condition MIN MAX Unit VDDSupply Voltage - 3.0 3.6 V Vt+ (Vp) Positive Going Threshold Voltage VOUT VOH (min)0.9 2.1 V Vt- (Vn) Negative Going Threshold Voltage VOUT VOL (max)0.7 1.9 V Vh (Vt) Hysteresis Voltage Vt+ - Vt- 0.2 1.4 V VOHOutput High Voltage IOH= -100 A IOH= -2 mA VDD-0.2 2.4

28、V VOLOutput Low Voltage IOL= 100 A IOL= 2 mA 0.2 0.4 V NOTE 1 VDDof the sending and receiving devices must track within 0.1V to maintain adequate dc margins. NOTE 2 For Vt+ (Vp) and Vt- (Vn), VDDrefers to the receiving device. For VOHand VOL, VDDrefers to the sending device. NOTE 3 Operating tempera

29、ture range as specified by manufacturer to be Commercial, Industrial and/or Military. JEDEC Standard No. 8C.01 Page 4 2.4 Optional DC electrical characteristics for Schmitt trigger operation (contd) 2.4.2 Optional Schmitt trigger operation Extended range Table 6 Input/Output Specification VDD (min)=

30、 2.7 V and VDD (max)= 3.6 V Symbol Parameter Test Condition MIN MAX Unit VDDSupply Voltage - 2.7 3.6 V Vt+ (Vp) Positive Going Threshold Voltage VOUT VOH (min)0.9 2.1 V Vt- (Vn) Negative Going Threshold Voltage VOUT VOL (max)0.7 1.9 V Vh (Vt) Hysteresis Voltage Vt+ - Vt- 0.2 1.4 V VOHOutput High Vol

31、tage IOH= -100 A VDD-0.2 V VOLOutput Low Voltage IOL= 100 A 0.2 V NOTE 1 VDDof the sending and receiving devices must track within 0.1V to maintain adequate dc margins. NOTE 2 For Vt+ (Vp) and Vt- (Vn), VDDrefers to the receiving device. For VOHand VOL, VDDrefers to the sending device. NOTE 3 Operat

32、ing temperature range as specified by manufacturer to be Commercial, Industrial and/or Military. 3 Test conditions for optional Schmitt trigger operation 3.1 Positive Going Threshold Voltage: Vt+ (Vp) As the input signal is raised from a ground level in the measurement circuit shown in Figure 1, the

33、 input voltage value at which the output logic changed is determined as Vt+ (Vp). 3.2 Negative Going Threshold Voltage: Vt- (Vn) As the input signal is dropped from a power supply voltage level in the measurement circuit shown in Figure 1, the input voltage value at which the output logic changed is

34、 determined as Vt- (Vn). Figure 1 DC characteristic measurement circuit of Schmitt trigger input JEDEC Standard No. 8C.01 Page 5 4 Background 4.1 Requirements of scaling To obtain better performance and higher density, semiconductor technologists are reducing the vertical and horizontal dimensions o

35、f integrated device structures. If constant supply voltages and interface levels are maintained, on-chip electric fields will increase and higher system level slew rates will lead to increased electromagnetic interference and device-induced noise such as ground bounce. Additionally, with increasing

36、numbers of on-chip functions, on-chip power dissipation may increase. All these factors - increased electric fields, electromagnetic interference, device-induced noise and power dissipation - lead to reduced reliability at the chip and system level. Thus, to continue the semiconductor scaling trend,

37、 a reduction of chip power supply voltage will be required. This JEDEC Standard will ease the transition from the existing 5 V 10% TTL standard by achieving agreement among the manufacturers and users. 4.2 LVTTL compatibility One justification for revising JEDEC Standard Nos. 8 and 8-1 is to maintai

38、n TTL compatibility with adequate noise margins. In addition, this standard is intended for components at all levels of integration. This will include memories, microprocessors, peripherals, standard logic functions, gate arrays, and programmable logic circuits. No preference for any implementation

39、technology is implied. Table 3 is intended to be LVTTL-compatible in the sense that the output logic 1 (VOH) and output logic 0 (VOL) levels have been specified at the same voltage levels that have been commonly recognized as logic 1 and logic 0 in the 5-V environment. Devices that meet the specific

40、ations in Tables 2 and 3 can generally be expected to drive 5-V “TTL-compatible” components. However, while 5-V “TTL-compatible” components should be able to meet the minimum input logic switching levels (VIHand VIL) of compounds that meet this standard, the logic-1 output voltage of many 5-V compen

41、diums will exceed the maximum input voltage of a Standard 8C compliant device. Depending on the technology and circuit implementation, the 5-V “TTL-compatible” components may drive their outputs anywhere from about 3 V to the VDDsupply level into a high-impedance load. CAUTION: Before connecting a 5

42、-V component to a 3-V or 3.3-V component, always check to be sure that the maximum VOHof the 5-V device does not exceed the specified VIHmaximum of the 3-V or 3.3-V device under the anticipated operating conditions. JEDEC Standard No. 8C.01 Page 6 4 Background (contd) 4.3 LVCMOS compatibility Compon

43、ents designed to meet the output requirement described in Table 4 of this standard are said to be “LVCMOS-compatible” because they are required to swing rail to rail under light dc load conditions in the manner commonly expected of “CMOS I/O” components. This feature facilitates the design of system

44、s for minimum static power consumption. In regard to CMOS input compatibility, Standard No. 8C components can also be said to be “CMOS-compatible” because: 1) The minimum VIHfor Standard 8C components is 2 V over the operating voltage range. Under the worst-case conditions for VIH, i.e., at VDD= max

45、, a VIHof 2 V is lower than the traditional CMOS VIHof 0.7 x VDD. The minimum guaranteed logic-1-level noise margin is 0.5 V (2.7 V -0.2 V -2.0 V) over the extended power supply range, 0.8 V (3.0 V -0.2 V -2.0 V) over the normal supply range, and 0.95 V (3.15 V -0.2 V -2.0 V) over the narrow supply

46、range. 2) The maximum VILfor components in this document is 0.8 V. Under the worst-case conditions for VIL, i.e., at VDD= min, a VILof 0.8 V is higher than the traditional CMOS VILof 0.2 x VDD. The minimum guaranteed logic-0-level noise margin is 0.6 V (0.8 V -0.2 V) over the power supply ranges. Th

47、erefore in all cases, Standard 8C compliant components exceed the traditional “CMOS I/O “logic level requirements. 4.4 Meeting Standard 8C requirements Components that meet the requirements of this standard shall meet the input specifications described in Table 2. Components are “LVTTL-compatible” i

48、f they meet the output specifications described in Table 3. Components are “LVCMOS-compatible” if they meet the output specifications described in Table 4. A component manufacturer may specify a device that meets both output specifications described in Tables 3 and 4. 4.5 Exceeding Standard 8C requi

49、rements Components may be specified in such a way as to exceed the requirements set forth in this standard. Such components may be said to “meet or exceed the requirements of JEDEC Standard No. 8C”. EXAMPLES 1 A component manufacturer of a 3.3-V device may specify a device to tolerate a 12-V signal as a logic high input, exceeding the Table 1 requirement that a 3.3-V device operate with VIH(max) of VDD+ 0.3 V. 2 A 3.3-V device may be specified to meet the Table 3 output logic levels while driving a considerably heavier 20-mA load, t