JEDEC JESD84-B51-2015 Embedded Multi-Media Card (e MMC) Electrical Standard (5 1).pdf

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1、JEDEC STANDARD Embedded Multi-Media Card (eMMC) Electrical Standard (5.1) JESD84-B51 (Revision of JESD84-B50.1, July 2014) FEBRUARY 2015 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC

2、Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of produc

3、ts, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their a

4、doption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications r

5、epresents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims t

6、o be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards a

7、nd Documents for alternative contact information. Published by JEDEC Solid State Technology Association 2015 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file

8、the individual agrees not to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid State Techn

9、ology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 84-B51 -i- EMBEDDED MULTI-MEDIA CARD (eMMC) 5.1 DEVICE Contents Page Foreword xx Introduction . xx 1 Scope . 1 2 Normative r

10、eference 1 3 Terms and definitions . 1 4 System Features . 4 5 eMMC Device and System 6 5.1 eMMC System Overview 6 5.2 Memory Addressing 6 5.3 eMMC Device Overview . 7 5.3.1 Bus Protocol 8 5.3.2 Bus Speed Modes 15 5.3.3 HS200 Bus Speed Mode 15 5.3.4 HS200 System Block Diagram 16 5.3.5 HS200 Adjustab

11、le Sampling Host . 16 5.3.6 HS400 Bus Speed Mode 16 5.3.7 HS400 System Block Diagram 17 6 eMMC functional description . 18 6.1 eMMC Overview . 18 6.2 Partition Management . 19 6.2.1 General 19 6.2.2 Command restrictions 21 6.2.3 Extended Partitions Attribute 21 6.2.4 Configure partitions . 22 6.2.5

12、Access partitions . 25 6.3 Boot operation mode . 25 6.3.1 Device reset to Pre-idle state . 25 6.3.2 Boot partition. 27 6.3.3 Boot operation . 28 6.3.4 Alternative boot operation . 29 6.3.5 Access to boot partition . 33 6.3.6 Boot bus width and data access configuration . 33 6.3.7 Boot Partition Writ

13、e Protection . 34 6.4 Device identification mode . 36 JEDEC Standard No. 84-B51 -ii- 6.4.1 Device reset . 36 6.4.2 Access mode validation (higher than 2GB of densities) . 37 6.4.3 From busy to ready 37 6.4.4 Device identification process 38 6.5 Interrupt mode . 38 6.6 Data transfer mode 40 6.6.1 Com

14、mand sets and extended settings 42 6.6.2 High-speed modes selection 43 6.6.3 “High-speed” mode selection 43 6.6.4 “HS200” timing mode selection 43 6.6.5 “HS400” timing mode selection 46 6.6.6 Power class selection . 49 6.6.7 Bus testing procedure 50 6.6.8 Bus Sampling Tuning Concept 51 6.6.9 Bus wid

15、th selection . 54 6.6.10 Data read . 54 6.6.11 Data write 56 6.6.12 Erase 59 6.6.13 TRIM 61 6.6.14 Sanitize 62 6.6.15 Discard 62 6.6.16 Secure Erase 64 6.6.17 Secure Trim . 65 6.6.18 Write protect management 66 6.6.19 Extended Security Protocols Pass Through Commands 68 6.6.20 Production State Aware

16、ness 69 6.6.21 Field Firmware Update 72 6.6.22 Device lock/unlock operation 73 6.6.23 Application-specific commands 76 6.6.24 Sleep (CMD5) . 77 6.6.25 Replay Protected Memory Block 78 6.6.26 Dual Data Rate mode selection . 92 6.6.27 Dual Data Rate mode operation 92 6.6.28 Background Operations . 93

17、6.6.29 High Priority Interrupt (HPI) . 94 6.6.30 Context Management 95 6.6.31 Data Tag Mechanism. 99 JEDEC Standard No. 84-B51 -iii- 6.6.32 Packed Commands 100 6.6.33 Exception Events . 102 6.6.34 Cache 103 6.6.35 Features cross matrix . 105 6.6.36 Dynamic Capacity Management . 106 6.6.37 Large sect

18、or size 107 6.6.38 Real Time Clock Information 111 6.6.39 Power Off Notification 112 6.6.40 Cache Enhancement Barrier 113 6.6.41 Cache Flushing Policy . 114 6.6.42 Command Queuing . 115 6.6.43 Secure Write Protect Mode . 120 6.7 Clock control . 121 6.8 Error conditions . 121 6.8.1 CRC and illegal co

19、mmand 121 6.8.2 Time-out conditions 122 6.8.3 Read ahead in multiple block read operation 123 6.9 Minimum performance 123 6.9.1 Speed class definition 123 6.9.2 Measurement of the performance 124 6.10 Commands . 124 6.10.1 Command types . 124 6.10.2 Command format . 124 6.10.3 Command classes 125 6.

20、10.4 Detailed command description 126 6.11 Device state transition table 134 6.12 Responses 136 6.13 Device status . 138 6.14 Memory array partitioning 142 6.15 Timings . 144 6.15.1 Command and response. 144 6.15.2 Data read . 146 6.15.3 Data write 147 6.15.4 Bus test procedure timing 151 6.15.5 Boo

21、t operation . 152 6.15.6 Alternative boot operation . 153 6.15.7 Timing Values . 154 JEDEC Standard No. 84-B51 -iv- 6.15.8 Timing changes in HS200 Device is busy programming . 150 Figure 52 Stop transmission after last data block; Device becomes busy 150 Figure 53 Bus test procedure timing . 151 Fig

22、ure 54 Boot operation, termination between consecutive data blocks . 152 Figure 55 Boot operation, termination during transfer . 152 Figure 56 Bus mode change timing (push-pull to open-drain) . 152 Figure 57 Alternative boot operation, termination between consecutive data blocks . 153 Figure 58 Alte

23、rnative boot operation, termination during transfer . 153 Figure 59 Clock Stop Timing at Block Gap in Read Operation . 156 Figure 60 Border Timing of CMD12 in Write Operation . 156 Figure 61 Border Timing of CMD12 in Read Operation 157 Figure 62 Enhanced Strobe signals for CMD Response and Data Out

24、(Read operation) . 158 Figure 63 Enhanced Strobe signals for CMD Response and CRC Response (Write operation) 158 Figure 64 HS400 mode change with Enhanced Strobe . 158 Figure 65 H/W reset waveform 159 Figure 66 Noise filtering timing for H/W reset 159 Figure 67 HS400 Write Timing with data block siz

25、e of 512 bytes . 160 Figure 68 HS400 Read Timing with data block size of 512 bytes 160 Figure 69 CRC7 generator/checker 234 Figure 70 CRC16 generator/checker 235 Figure 71 Bus circuitry diagram . 236 Figure 72 Power-up diagram 237 Figure 73 eMMC power-up diagram . 239 Figure 74 eMMC power cycle. 241

26、 Figure 75 eMMC bus driver 243 Figure 76 eMMC internal power diagram (as an example) . 244 Figure 77 e2MMC internal power diagram (as an example) . 245 JEDEC Standard No. 84-B51 -xiv- Figure 78 HS400 reference load . 248 Figure 79 Overshoot/Undershoot definition . 249 Figure 80 Bus signal levels . 2

27、49 Figure 81 Outputs test circuit for rise/fall time measurement. 252 Figure 82 Timing diagram: data input/output . 253 Figure 83 Timing diagram: data input/output in dual data rate mode . 255 Figure 84 HS200 Clock signal timing 257 Figure 85 HS200 Device input timing 258 Figure 86 HS200 Device outp

28、ut timing 259 Figure 87 TPH consideration 260 Figure 88 HS400 Device Data input timing . 261 Figure 89 HS400 Device output timing 262 Figure 90 HS400 CMD Response timing . 264 Figure A.91 Legend for command-sequence flow charts . 270 Figure A.92 SEND_OP_COND command flow chart . 271 Figure A.93 CIM_

29、SINGLE_DEVICE_ACQ . 272 Figure A.94 CIM_SETUP_DEVICE 273 Figure A.95 CIM_READ_BLOCK 274 Figure A.96 CIM_READ_MBLOCK . 274 Figure A.97 CIM_WRITE_MBLOCK . 275 Figure A.98 CIM_ERASE_GROUP 276 Figure A.99 CIM_TRIM 277 Figure A.100 CIM_US_PWR_WP . 278 Figure A.101 CIM_US_PERM_WP . 279 Figure A.102 Erase-

30、unit size selection flow . 285 Figure A.103 Stop transmission just before CRC status transfer from the device 287 Figure A.104 Stop transmission during CRC status transfer from the device 287 Figure A.105 Stop transmission during CRC status transfer from the device 288 Figure A.106 Heat Removal - No

31、menclatures 289 Figure A.107 FFU flow 292 Figure A.108 CMD44+CMD45 flow . 293 Figure A.109 CMD46+CMD47 flow . 294 Figure B.110 Proposed Host System Architecture, with CQE . 297 Figure B.111 Command Queuing HCI General Architecture . 298 Figure B.112 Task Queuing Sequence . 322 Figure B.113 Task Exec

32、ution and Completion Sequence . 323 Figure B.114 Task Discard and Clear Sequence Diagram 324 Tables Page Table 1 eMMC Voltage Modes . 4 Table 2 eMMC interface . 7 Table 3 eMMC registers 8 Table 4 Bus Speed Modes 15 Table 5 CMD line modes overview 18 Table 6 EXT_CSD access mode . 42 Table 7 Bus testi

33、ng pattern . 50 JEDEC Standard No. 84-B51 -xv- Table 8 1-bit bus testing pattern . 50 Table 9 4-bit bus testing pattern . 51 Table 10 8-bit bus testing pattern . 51 Table 11 Erase command (CMD38) Valid arguments 60 Table 12 Erase command (CMD38) Valid arguments 64 Table 13 Write Protection Hierarchy

34、 (when disable bits are clear) 67 Table 14 Write Protection Types (when disable bits are clear) 67 Table 15 Security Protocol Information . 69 Table 16 Lock Device data structure 73 Table 17 Data Frame Files for RPMB 78 Table 18 RPMB Request/Response Message Types 79 Table 19 RPMB Operation Results

35、data structure 79 Table 20 RPMB Operation Results 80 Table 21 MAC Example . 82 Table 22 Authentication Key Data Packet 83 Table 23 Result Register Read Request Packet 84 Table 24 Response for Key Programming Result Request . 84 Table 25 Counter Read Request Packet 85 Table 26 Counter Value Response

36、85 Table 27 Program Data Packet . 86 Table 28 Result Register Read Request Packet 87 Table 29 Response for Data Programming Result Request 87 Table 30 Data Read Request Initiation Packet . 88 Table 31 Read Data Packet . 88 Table 32 Authenticated Device Configuration Write packet 89 Table 33 Response

37、 for Authenticated Device Configuration Write Request 90 Table 34 Authenticated Device Configuration Read Initiation packet . 91 Table 35 Response for Authenticated Device Configuration Read 91 Table 36 Interruptible commands . 94 Table 37 Packed Command Structure 101 Table 38 Features Cross Referen

38、ce Table 105 Table 39 eMMC internal sizes and related Units / Granularities 108 Table 40 Admitted Data Sector Size, Address Mode and Reliable Write granularity 110 Table 41 Real Time Clock Information Block Format . 111 Table 42 RTC_INFO_TYPE Field Description . 111 Table 43 Task Management op-codes

39、 117 Table 44 Error handling for Command Queue . 118 Table 45 Supported Commands for Command Queue . 119 Table 46 Device Configuration Area 120 Table 47 Command Format 124 Table 48 Supported Device command classes (056) 125 Table 49 Basic commands (class 0 and class 1) . 126 Table 50 Block-oriented

40、read commands (class 2) . 127 Table 51 Class 3 commands . 127 Table 52 Block-oriented write commands (class 4) 128 Table 53 Block-oriented write protection commands (class 6) 129 Table 54 Erase commands (class 5) 130 JEDEC Standard No. 84-B51 -xvi- Table 55 I/O mode commands (class 9) . 131 Table 56

41、 Lock Device commands (class 7) 131 Table 57 Application-specific commands (class 8) 131 Table 58 Security Protocols (class 10) . 132 Table 59 Command Queue (Class 11) 133 Table 60 Device state transitions 134 Table 61 Device state transitions (contd) 135 Table 62 Device state transitions (contd) 13

42、6 Table 63 R1 response . 136 Table 64 R2 response . 137 Table 65 R3 Response 137 Table 66 R4 response . 137 Table 67 R5 response . 137 Table 68 Device status 139 Table 69 Device Status field/command - cross reference . 141 Table 70 Response 1 Status Bit Valid 142 Table 71 Timing Parameters . 154 Tab

43、le 72 Timing Parameters for HS200 and HS400 mode. 155 Table 73 H/W reset timing parameters . 159 Table 74 OCR register definitions 161 Table 75 CID Fields . 162 Table 76 Device Types . 162 Table 77 Valid MDT “y” Field Values . 163 Table 78 CSD Fields . 164 Table 79 CSD register structure . 165 Table

44、 80 System specification version . 165 Table 81 TAAC access-time definition 165 Table 82 Maximum bus clock frequency definition . 166 Table 83 Supported Device command classes 166 Table 84 Data block length . 166 Table 85 DSR implementation code table 167 Table 86 VDD (min) current consumption . 168

45、 Table 87 VDD (max) current consumption 168 Table 88 Multiplier factor for device size. 169 Table 89 R2W_FACTOR . 170 Table 90 File formats 171 Table 91 ECC type . 171 Table 92 CSD field command classes 172 Table 93 Extended CSD . 173 Table 94 EXT_SECURITY_ERR byte description 178 Table 95 Device-su

46、pported command sets . 178 Table 96 HPI features . 178 Table 97 Background operations support . 179 Table 98 Context Management Context Capabilities . 180 Table 99 Extended CSD Register Support 180 Table 100 SUPPORTED_MODES 180 Table 101 FFU FEATURES . 180 JEDEC Standard No. 84-B51 -xvii- Table 102

47、MODE_OPERATION_CODES timeout definition 181 Table 103 Device life time estimation type B value . 182 Table 104 Device life time estimation type A value . 183 Table 105 Pre EOL info value 183 Table 106 Optimal read size value . 184 Table 107 Optimal write size value 184 Table 108 Optimal trim unit si

48、ze value 184 Table 109 Generic Switch Timeout Definition . 185 Table 110 Power off long switch timeout definition 185 Table 111 Background operations status 186 Table 112 Correctly programmed sectors number 186 Table 113 Initialization Time out value 186 Table 114 Cache Flushing Policy . 187 Table 115 TRIM/DISCARD Time out value 187 Table 116 SEC Feature Support . 188 Table 117 Secure Erase time-out value 189 Table 118 Secure Erase time-out value 189 Table 119 Boot information 190 Table 120 Boot partition s