JEDEC JESD8-30-2017 POD125 - 1 25 V Pseudo Open Drain I O.pdf
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1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD8-30SEPTEMBER 2017JEDECSTANDARDPOD125 - 1.25 V Pseudo OpenDrain I/ONOTICEJEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by t
2、he JEDEC legal counsel.JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minim
3、um delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally.JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. By s
4、uch action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications.The information included in JEDEC standards and publications represents a sound approach to product specification and application, pr
5、incipally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard.No claims to be in conformance with this standard may be made unless all requiremen
6、ts stated in the standard are met.Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Documents for alternative contact information.Published byJEDEC Solid
7、State Technology Association 20173103 North 10th StreetSuite 240 SouthArlington, VA 22201-2107This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material.PRICE:
8、 Contact JEDECPrinted in the U.S.A. All rights reservedPLEASE!DONT VIOLATETHELAW!This document is copyrighted by JEDEC and may not bereproduced without permission.For information, contact:JEDEC Solid State Technology Association3103 North 10th StreetSuite 240 SouthArlington, VA 22201-2107or refer to
9、 www.jedec.org under Standards-Documents/Copyright Information.JEDEC Standard No. 8-30Page 1POD125 - 1.25 V PSEUDO OPEN DRAIN I/O(From JEDEC Board Ballot JCB-17-25, formulated under the cognizance of the JC-16 Committee on Interface Technology.)1 ScopeThis standard defines the DC and AC single-ended
10、 (data) and differential (clock) operating conditions, I/O impedances, and the termination and calibration scheme for 1.25 V Pseudo Open Drain I/Os.The 1.25 V Pseudo Open Drain interface, also known as POD125, is primarily used to communicate with GDDR6 SGRAM devices.Multiple Classes of POD125 are e
11、xpected to reside within the family of POD125 interfaces in order to accommodate various device and market applications. The various classes standardized within the context of POD125 are documented in the appendices of this document (e.g., POD125/Class A).The core of this standard documents the subs
12、et of values common to all Classes of POD125 and documents specification items left to definition within a specific Class as denoted by CDV which is defined as Class Dependent Value.The values specific to each particular class of POD125 are found in the annexes. See specific Class tables for further
13、 details.NOTE It does not follow that all specification values defined in a given Class are necessarily different from the matching parameter in other Class within POD125. Multiple Classes may reuse a given specification value if appropriate to the Class requirements.JEDEC Standard No. 8-30Page 22 C
14、ore POD125 Interface StandardTable 1 DC Operating ConditionsParameter SymbolPOD125Unit NotesMin Typ MaxDevice Supply Voltage VDD1.2125 1.25 1.2875 V 1Output Supply Voltage VDDQ1.2125 1.25 1.2875 V 1Reference voltage: DQ and DBI_n pinsReference voltage: CA pinsDC input logic HIGH voltage with VREFC:
15、CADC input logic LOW voltage with VREFC: CADC input logic HIGH voltage with VREFC2: CADC input logic LOW voltage with VREFC2: CADC input logic HIGH voltage with VREFD: DQ, DBI_nDC input logic LOW voltage with VREFD: DQ, DBI_nDC input logic HIGH voltage with VREFD2: DQ, DBI_nDC input logic LOW voltag
16、e with VREFD2: DQ, DBI_nRESET_n and boundary scan input logic HIGH voltage; EDC and CA input logic high voltage for x16/x8 mode, PC vs. 2-channel mode, CK and CA ODT select at resetRESET_n and boundary scan input logic LOW voltage; EDC and CA input logic low voltage for x16/x8 mode, PC vs. 2-channel
17、 mode, CK and CA ODT select at resetInput leakage current (any input 0V = VIN= VDDQ; all other signals not under test = 0V) Output leakage current (outputs are disabled;0V = VOUT= VDDQ)Output logic LOW voltage VOL(DC) 0.52 VSingle ended clock input voltage level: CK_t, CK_c, WCK_t, WCK_cClock input
18、mid-point voltage: CK_t, CK_cClock input differential voltage: CK_t, CK_cClock input differential voltage: WCK_t, WCK_cNOTE 2 DC bandwidth is limited to 20 MHz.NOTE 3 AC noise in the system is estimated at 50mV pk-pk for the purpose of DRAM design.NOTE 4 The reference voltage source and control for
19、DQ and DBI_n pins are determined by Half VREFDand VREFDLevel mode register bits.NOTE 5 Programmable VREFDlevels are not supported with VREFD2.NOTE 6 The reference voltage source (external or internal) is determined at power-up; the reference voltage level is determined by Half VREFCand the VREFCOffs
20、et mode register bits. NOTE 7 Programmable VREFCoffsets are not supported with VREFC2.NOTE 8 VIHRand VILRapply to boundary scan input pins TDI, TMS and TCK. VIHRand VILRapply to EDC and CA inputs at reset when latching default device configurations. VIHRand VILRalso apply to CA, CABI_n, CKE_n, CK, D
21、Q, DBI_n, EDC and WCK inputs when boundary scan mode is active and input data are latched in the Capture-DR TAP controller state.NOTE 9 This provides a minimum of 0.775 V to a maximum of 0.975 V, and is normally 70% of VDDQ. DRAM timings relative to CK_t cannot be guaranteed if these limits are exce
22、eded.NOTE 10 VIDCKis the magnitude of the difference between the input level in CK_t and the input level on CK_c. The input reference level for signals other than CK_t and CK_c is VREFC.NOTE 11 VIDWCKis the magnitude of the difference between the input level in WCK_t and the input level on WCK_c. Th
23、e input reference level for signals other than WCK_t and WCK_c is either VREFC, VREFC2, VREFDor VREFD2.NOTE 12 The CK_t and CK_c input reference level (for timing referenced to CK_t and CK_c) is the point at which CK_t and CK_c cross. Please refer to the applicable timings in the AC Timings table.NO
24、TE 13 Use VIHRand VILRwhen boundary scan mode is active and input data are latched in the Capture-DR TAP controller state.NOTE 14 The WCK_t and WCK_c input reference level (for timing referenced to WCK_t and WCK_c) is the point at which WCK_t and WCK_c cross. Please refer to the applicable timings i
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