JEDEC JESD35-A-2001 Procedure for the Wafer-Level Testing of Thin Dielectrics《薄电介质的Wafer-Level测试程序》.pdf
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1、JEDECSTANDARDProcedure for the Wafer-Level Testingof Thin DielectricsJESD35-A(Revision of JESD35)APRIL 2001JEDEC Solid State technology AssociationNOTICEJEDEC standards and publications contain material that has been prepared, reviewed, andapproved through the JEDEC Board of Directors level and subs
2、equently reviewed and approvedby the EIA General Counsel.JEDEC standards and publications are designed to serve the public interest through eliminatingmisunderstandings between manufacturers and purchasers, facilitating interchangeability andimprovement of products, and assisting the purchaser in se
3、lecting and obtaining with minimumdelay the proper product for use by those other than JEDEC members, whether the standard is tobe used either domestically or internationally.JEDEC standards and publications are adopted without regard to whether or not their adoptionmay involve patents or articles,
4、materials, or processes. By such action JEDEC does not assumeany liability to any patent owner, nor does it assume any obligation whatever to parties adoptingthe JEDEC standards or publications.The information included in JEDEC standards and publications represents a sound approach toproduct specifi
5、cation and application, principally from the solid state device manufacturerviewpoint. Within the JEDEC organization there are procedures whereby an JEDEC standard orpublication may be further processed and ultimately become an ANSI/EIA standard.No claims to be in conformance with this standard may
6、be made unless all requirements stated inthe standard are met.Inquiries, comments, and suggestions relative to the content of this JEDEC standard orpublication should be addressed to JEDEC Solid State Technology Association, 2500 WilsonBoulevard, Arlington, VA 22201-3834, (703)907-7560/7559 or www.j
7、edec.orgPublished byJEDEC Solid State Technology Association 20002500 Wilson BoulevardArlington, VA 22201-3834This document may be downloaded free of charge, however EIA retains thecopyright on this material. By downloading this file the individual agrees not tocharge for or resell the resulting mat
8、erial.PRICE: Please refer to the currentCatalog of JEDEC Engineering Standards and Publications or call Global EngineeringDocuments, USA and Canada (1-800-854-7179), International (303-397-7956)Printed in the U.S.A.All rights reservedPLEASE!DONT VIOLATETHELAW!This document is copyrighted by the Elec
9、tronic Industries Alliance and may not bereproduced without permission.Organizations may obtain permission to reproduce a limited number of copiesthrough entering into a license agreement. For information, contact:JEDEC Solid State Technology Association2500 Wilson BoulevardArlington, Virginia 22201
10、-3834or call (703) 907-7559JEDEC Standard No. 35-A-i-PROCEDURE FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICSCONTENTSPageForeword ii1Scope 12 Introduction 12.1 Overview 12.1 Choosing the appropriate stress procedures 13 Terms and definitions 24 V-ramp test procedure 44.1 Test configuration 44.2 V-R
11、amp input and output parameters 44.3 Pre-Ramp oxide current test 64.4 Ramp voltage stress 64.5 Post-ramp oxide current test 104.6 Data recording 114.7 Oxide failure categories 115 J-Ramp test procedure 125.1 Test configuration 125.2 J-Ramp input and output parameters 125.3 Pre-Ramp oxide test 145.4
12、J-Ramp stress test 175.5 Bounded J-Ramp 195.6 Post-ramp oxide test 215.7 Data recording 215.8 Oxide failure categories 226 References 23Annex A Supplemental data analysis 24A.1 Overview 24A.2 Data analysis 24A.3 Defect source analysis 27Annex B Supplemental Sampling plan statistics 29B.1 Overview 29
13、B.2 Determining an acceptable defect density level 30B.3 Sampling required to demonstrate defect densities 32B.4 Determining defect density from a test result 34B.5 Ensuring acceptable edge defect densities 35B.6 Examples for use of defect density curves 35Annex C Fowler-Nordheim tunneling current 4
14、0C.1 Fowler-Nordheim 40Figures4.1 Basic voltage-ramp flow diagram 74.2 Detailed voltage-ramp flow diagram 84.3 Diagram of typical voltage-ramp test 95.1 Basic J-Ramp flow diagram 155.2 Detailed J-Ramp flow diagram 165.3 Diagram of typical J-Ramp test 185.4 Detailed bounded J-Ramp flow diagram 20Tabl
15、es4.1 Input parameters for the V-Ramp test procedure 54.2 Output parameters for the V-Ramp test procedure 64.3 Oxide failure categories 125.1 Input parameters for the J-Ramp test procedure 135.2 Output parameters for the J-Ramp test procedure 135.3 Oxide failure categories 22JEDEC Standard No. 35-A-
16、ii-PROCEDURE FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICSForewordThis document is intended for use in the MOS Integrated Circuit manufacturing industryfabrication processing and test and describes procedures developed for estimating the overallintegrity of thin oxides. Three basic test procedures
17、 are described, the Voltage-Ramp (V-Ramp),the Current-Ramp (J-Ramp) and the Constant Current (Bounded J-Ramp) test. Each test isdesigned for simplicity, speed and ease of use.The purpose of this document is to describe oxide test techniques for quick evaluation andcontrol of oxide fabrication techni
18、ques. It does not specify acceptance or rejection criteria forany of the described procedures and therefore not intended to be used to predict MOS IntegratedCircuit failure rates.The material contained within this publication is formulated under the cognizance of JEDECJC-14.2 Committee and approved
19、by the JEDEC Board of Directors.JEDEC Standard No. 35-APage 1PROCEDURE FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICS(From JEDEC Board Ballot JCB-99-24, formulated under the cognizance of JEDEC JC-14.2Subcommittee on Wafer Level Reliability)1ScopeThis document defines test procedures for the V-Ramp
20、, J-Ramp and the Bounded J-Ramp oxideintegrity tests. Included within this document are recommended data analysis methods andguidelines for statistical sampling.2 Introduction2.1 OverviewThe thin dielectric integrity of MOS devices and circuits is an important reliability concern.Historically, thin
21、oxide reliability has been driven by oxide defects. In general the intrinsic oxidelifetime is much longer than the use requirements, but defects can significantly reduce oxidelifetime. The procedures described herein were developed to estimate the integrity of a thinoxide and as a tool for driving c
22、onstant improvement in the thin oxide process.The test procedures described within this document should not used to predict failure rates of asemiconductor product but rather tools for process control of oxide integrity. In actual practicethe oxide reliability of a semiconductor product is a complic
23、ated function of individual transistorduty cycles, transient voltage variation, the gate graded potential and series resistance in the gateload. These parameters are not considered within this document.2.2 Choosing the appropriate stress proceduresThree test procedures are described within this docu
24、ment; a ramped voltage (V-Ramp), a rampedcurrent (J-Ramp) and a constant current (Bounded J-Ramp) test. Each of these procedures isdesigned for simplicity, speed and ease of use and can be implemented at each point in theprocess from oxide formation onward.The voltage ramp test (V-Ramp) starts at th
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