JEDEC JESD286-B-2000 Standard for Measuring Forward Switching Characteristics of Semiconductor Diodes《测量半导体二极管前向交换特性的标准》.pdf
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1、JEDECSTANDARDStandard for Measuring ForwardSwitching Characteristics ofSemiconductor DiodesJESD286-B(Revision of EIA-286-A)FEBRUARY 2000: Reaffirmed April 2005ELECTRONIC INDUSTRIES ALLIANCEJEDEC Solid State Technology AssociationNOTICEEIA/JEDEC standards and publications contain material that has be
2、en prepared, reviewed, andapproved through the JEDEC Board of Directors level and subsequently reviewed and approved bythe EIA General Counsel.EIA/JEDEC standards and publications are designed to serve the public interest through eliminatingmisunderstandings between manufacturers and purchasers, fac
3、ilitating interchangeability andimprovement of products, and assisting the purchaser in selecting and obtaining with minimum delaythe proper product for use by those other than JEDEC members, whether the standard is to be usedeither domestically or internationally.EIA/JEDEC standards and publication
4、s are adopted without regard to whether or not their adoptionmay involve patents or articles, materials, or processes. By such action JEDEC does not assume anyliability to any patent owner, nor does it assume any obligation whatever to parties adopting theEIA/JEDEC standards or publications.The info
5、rmation included in EIA/JEDEC standards and publications represents a sound approachto product specification and application, principally from the solid state device manufacturerviewpoint. Within the JEDEC organization there are procedures whereby an EIA/JEDEC standardor publication may be further p
6、rocessed and ultimately become an ANSI/EIA standard.No claims to be in conformance with this standard may be made unless all requirements stated in thestandard are met.Inquiries, comments, and suggestions relative to the content of this EIA/JEDEC standard orpublication should be addressed to JEDEC S
7、olid State Technology Association, 2500 WilsonBoulevard, Arlington, VA 22201-3834, (703)907-7560/7559 or www.jedec.orgPublished byELECTRONIC INDUSTRIES ALLIANCE 1999JEDEC Solid State Technology Association2500 Wilson BoulevardArlington, VA 22201-3834This document may be downloaded free of charge, ho
8、wever EIA retains thecopyright on this material. By downloading this file the individual agrees not tocharge or resell the resulting material.PRICE: Please refer to the currentCatalog of JEDEC Engineering Standards and Publications or call Global EngineeringDocuments, USA and Canada (1-800-854-7179)
9、, International (303-397-7956)Printed in the U.S.A.All rights reservedPLEASE!DON”T VIOLATETHELAW!This document is copyrighted by the Electronic Industries Alliance and may not bereproduced without permission.Organizations may obtain permission to reproduce a limited number of copiesthrough entering
10、into a license agreement. For information, contact:JEDEC Solid State Technology Association2500 Wilson BoulevardArlington, Virginia 22201-3834or call (703) 907-7559JEDEC Standard No. 286-BPage 1STANDARD FOR MEASURING FORWARD SWITCHING CHARACTERISTICS OFSEMICONDUCTOR DIODES(From JEDEC Board Ballot JC
11、B-99-13 formulated under the cognizance of JEDEC JC-22.4 Committee onSignal and Regulator Diodes.)1 Forward switching characteristicsWhen a step function of forward current (high di/dt) is applied to a signal or switching diode (typicallyrated less than 400 mA and less than 150 volts), the carrier g
12、radient does not develop immediately,resulting in an overshoot voltage that decreases with time to the dc static level. The diode appears to beinductive; however, transit time and conductivity modulation, not inductance, are responsible for theeffect. The result is an overshoot voltage that decays t
13、o the normal forward voltage in a measurable time. This phenomenon is called forward recovery as described in Section 2 of this Standard.Forward current-time characteristics are sometimes considered in respect to propagation delay from diodesin low-impedance, low-voltage, high-speed signal circuits.
14、 In these circuits, the transit time andmodulation result in delayed conduction of forward current instead of the forward recovery response notedabove. This behavior relates to turn-on time as described in Section 3 of this Standard.Both the voltage overshoot and delayed conduction are from the same
15、 forward switching phenomenon. Since the circuits that exhibit such behavior are different in observed response, one must use different testmethods; both are given in this Standard.2 Forward recoveryForward Recovery Time, (tfr), is the time interval between the instant when the forward voltage rises
16、through a specified first value, usually 10% of its final value, and the instant when it falls from its peakvalue, VFRM, to a specified low second value, vFR, upon the application of a step current following a zerovoltage or a specified reverse voltage condition.Peak forward recovery voltage, VFRM,
17、is the maximum instantaneous value across the DUT resulting fromthe application of a specified step function of forward current. This characteristic is sometimes referred toas modulation voltage. Also VF(pk), VFM(DYN), and VFMare sometimes used, but VFRMis preferred.2.1 ProcedureThe DUT is subjected
18、 to a specified step function of forward current. The resulting current waveformthrough the device and voltage waveform across the device are graphically monitored with amplitudedisplayed versus time. The desired characteristics are obtained from the display.JEDEC Standard No. 286-BPage 22 Forward r
19、ecovery (contd)2.2 Test circuit and waveformThe general test circuit is shown in Figure 1 and the waveforms in Figure 2.The current pulse source may be a pulse generator, charged line, pulse-forming network, or the like. If thenature of the source requires an internal switch, devices such as a mercu
20、ry switch, power MOSFET orsimilar devices may be used. Compliance voltage (open circuit output voltage) of the pulse current sourceshall be a minimum 3 VFRM. In any event, the combination must provide the specified conditions of thepulse to the DUT.Aberrations of the pulse top shall not exceed +10%
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