JEDEC JESD22-A122A-2016 Power Cycling.pdf

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1、JEDEC STANDARD Power Cycling JESD22-A122A (Revision of JESD22-A122, August 2007) JUNE 2016 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently revi

2、ewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting a

3、nd obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, mater

4、ials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product specific

5、ation and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in conformance with this standard may be

6、made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Documents for alternative contact informati

7、on. Published by JEDEC Solid State Technology Association 2016 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or res

8、ell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite

9、 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 22-A122A -i- TEST METHOD A122A POWER CYCLING Foreword This document provides an industry standard test method for power cycling of solid state device packages where on an

10、d off cycles of a device create a non-uniform temperature distribution within the package and the next level of assembly. Both sleep and full power modes can be simulated and are used as the basis of life cycle testing of the solid state device and/or associated interconnections. Introduction In typ

11、ical use, the on and off power cycles of functional devices will produce non-uniform temperature distributions within package components as well as between the package and interconnected hardware such as printed wiring boards (PWB), sockets, or heat sinks. The stresses that result from the temperatu

12、re gradients found in actual product may or may not be accurately simulated by use of isothermal temperature cycling. This test method is a characterization tool which can augment and supplement results obtained with the isothermal chamber-based temperature cycling described in both JESD22-A104 and

13、JESD22-A105. It should be used as an alternative to JESD22-A104 or JESD22-A105 only if such substitution can be technically justified. The test method uses a powered device, a thermal chip or an external heat source to simulate temperature cycling effects on the solid state device package and its ma

14、terials, including solder joints in free-standing and assembled configurations. Unlike either JESD22-A104 or JESD22-A105, the power cycles described in this test method are intended to simulate the range of usage conditions found from the vicinity of room ambient up to Tj maximum for the device, and

15、 are not specifically intended as a highly accelerated test or to apply to harsh application conditions such as those used to simulate some under-hood or aerospace environments. JEDEC Standard No. 22-A122 -ii- JEDEC Standard No. 22-A122A Page 1 Test Method A122 TEST METHOD A122 POWER CYCLING (From J

16、EDEC Board Ballot JCB-16-20, formulated under the cognizance of the JC-14.1 Subcommittee on Reliability Test methods for packaged Devices.) 1 Scope This Test Method establishes a uniform method for performing solid state device package power cycling stress test. This specification covers power induc

17、ed temperature cycling of a packaged component, simulating the non-uniform temperature distribution resulting from a device powering on and off in the application. This test is conducted to determine the ability of solid state device to withstand thermal-mechanical stresses induced by cyclic, non-is

18、othermal high and low temperatures induced by the device operation, including options like standby, hibernate or mini cycles found in some applications. It is used to verify the performance of various component materials and interfaces, especially solder interconnects and thermal interface materials

19、 (TIM). Both engineering samples with internal or external thermal heaters and actual power driven product can be used in this test method. Permanent changes in electrical and/or physical characteristics can result from these mechanical stresses and as such should be considered a destructive test. 2

20、 Terms and definitions 2.1 Tj (test) The temperature of the powered during the heating cycle 2.2 Temperature distribution characterization The range of temperature measured at key points of interest on the solid state device or its associated hardware and signified by T1, T2, etc., see Figure A.1. 2

21、.3 Maximum cycle temperature: Tcycle(max)The maximum cycle temperature of the test, see Table 2. 2.4 Minimum cycle temperature: Tcycle(min)The minimum temperature of the test 2.5 T (ambient) The temperature of the local ambient around the test hardware JEDEC Standard No. 22-A122A Page 2 Test Method

22、A122A (Revision of A122) 2 Terms and definitions (contd) 2.6 Nominal T The difference between nominal Tcycle(max)and nominal Tcycle(min)for the Power Cycling Test Condition, see Figure A.1. 2.7 soak time: The total time the temperature of the sample is within a specified range of each nominal Tcycle

23、(max)and nominal Tcycle(min). This range is defined as the time Tjis at 5 C to +10 C of Tcycle(max)nominal for the upper end of the cycle and the time Tj is +5 C to 10 C of Tcycle(min)nominal for the lower end of the cycle. 2.8 Cycle time Time between one high temperature extreme to the next, or fro

24、m one low temperature extreme to the next, for a given sample, see Figure A.1. 3 Apparatus The apparatus used shall be capable of providing and controlling the specified temperatures and cycle timing. While the objective, test samples, and general procedures are similar to accelerated thermal cyclin

25、g in a chamber, there are also important differences. Key elements of a power cycle apparatus include the following and are illustrated in Figure A.2. a) A heating element for each tested sample. The heating method and location of heat source will be dependent on the test objective, and can include,

26、 but is not limited to, a powered device in the actual product, a serpentine line in the package, a thermal test chip, or an attached external heater mounted on or within the module. NOTE Dependent on the test point of interest for the solid state device or its associated hardware, the appropriate h

27、eating method and location should be used such that the results are representative of the application. b) Power supplies and connections for powering the heater elements or other heat source. c) A housing or fixture for each sample or group of samples to provide electrical connections for powering a

28、nd/or monitoring, and to facilitate cooling. d) Computer, relay box, or other method of controlling heating and cooling to specified heat and cool parameters. e) Ambient condition, controlled to the specified temperature range and/or air flow, which can consist of either the surrounding room or a lo

29、cal test enclosure. f) Cooling system, including forced air or other means, dependent on the application and/ or test requirements. g) Data collection system capable of recording pertinent test data, including temperature and electrical test information and results. JEDEC Standard No. 22-A122A Page

30、3 Test Method A122 4 Procedure The procedure for power cycle testing of solid state device packages generically consists of running the device under test (DUT) through a prescribed temperature range, for a given number of cycles, with appropriate data collection during the test. This cycling period

31、usually starts with a setup step where the device is powered and the cycle temperatures are adjusted and verified. Some typical temperature ranges are shown in Table 2, though other temperatures ranges can be used, based on the specific application requirements. Key elements to an effective procedur

32、e include, but are not limited to, test controls, temperature measurement methodology, data collection requirements and heating/ cooling methods. These will be discussed in greater detail in the following clauses. 4.1 Test samples, fixtures, and associated hardware The entire power cycle test config

33、uration, including device, package, heat sink, printed circuit board thickness, and fixturing will have a significant effect on results. The test can be done with either actual product or a development test vehicle designed to simulate product. For application specific qualifications, the power cycl

34、ing setup should reflect the actual product situation as close as possible. 4.2 Power cycling methods There are a number of ways that power cycling can be performed. This includes use of constant or variable prescribed power and constant or variable heat removal or cooling, or combinations of these.

35、 a) Constant power: For any single heater/ device, power is either ON (to a preset value, during heat up) or OFF (during cooling). This usually involves open loop control. The preset value may be varied among DUT to compensate for heater differences and improve temperature uniformity. b) Variable po

36、wer: Power varies during the heating and/ or cooling cycle to allow faster heat ramps, mini-cycles and/ or standby modes. Closed loop control is recommended. c) Constant cooling: As with constant power, cooling is either ON (to a preset value during cooling or throughout the entire cycle) or OFF (du

37、ring heating, as prescribed). This option involves open loop control. d) Variable cooling: Cooling varies during the heating and/ or cooling cycle to allow mini-cycles, standby mode options or to mimic other system conditions. Use of this option can also enable increasing the cycle rate. Figure 1 il

38、lustrates the example of constant versus variable power with constant cooling. Table 1 discusses the advantages and disadvantages of each combination. The specific combination used should be selected on product requirements and should be noted as part of the test summary. JEDEC Standard No. 22-A122A

39、 Page 4 Test Method A122A (Revision of A122) 4 Procedure (contd) 4.2 Power cycling methods (contd) There are a number of methods to apply heat to the device under test (DUT). The most common are either a powered device in the actual product, a serpentine line in the package, or an attached external

40、heater mounted on or within the module. Similarly cooling can be through forced convection (air, water or liquid nitrogen under controlled meter), natural convection or by means of attached cooling devices such as, but not limited to, thermoelectric coolers, Peltier cooling plates, or heat pipes. It

41、 should be noted that air cooling with a heat sink may be slow and affect test duration and test cycle frequency. PowerCoolingTemperatureConstant Power / Constant CoolingPowerCoolingTemperatureVariable Power / Constant CoolingFigure 1 Comparison of constant versus variable power testing JEDEC Standa

42、rd No. 22-A122A Page 5 Test Method A122 4 Procedure (contd) 4.2 Power cycling methods (contd) Table 1 Power Cycling Methods Test Setup Options Constant Heat Removal/ Cooling Variable heat Removal/ Cooling Constant Power Easiest to implement Requires attention to test detail Best suited for functiona

43、l device testing Best suited for test vehicles with tightly controlled heater resistances If power must be held constant, variable cooling can allow Tj variation and acceleration modeling Vary ambient temperatures to simulate different environments Could be used for mini-cycle evaluation Variable Po

44、wer Ramping power to test site closely matches actual product profile Need control to prevent unrealistic power surge Could be used for mini-cycle evaluations Different heating patterns, such as, multiple heaters with different resistances can be turned on at different intervals to match thermal pro

45、file found in actual product Most difficult to implement since it requires significant software control capability Most appropriate for power cycling of products with complex chip power maps and cooling requirements Can be used extensively in power cycle set-up and debug, while honing in on desired

46、power/ temperature profile 4.3 Test hardware The DUT can consist of either functional product or simulated product through use of test vehicles. Selection should be made based on test hardware availability and the specific test point of interest; e.g. interconnections, thermal interface, etc. If tes

47、t vehicles are used they should be designed such that all relevant package and chip to package interaction failure mechanisms can be evaluated during the testing. Heaters should be positioned in the device such that the test site heating is similar to that seen in the product. Dependent on the test

48、site of interest, the temperature variation across the test or functional die can be very important in assessing the product performance in the field. Temperature sensors should be located across the DUT, either functional or test vehicle, to measure temperature variations on test hardware, see JEP

49、140 “Beaded Thermocouple Measurement of Semiconductor Packages” for one method of temperature measurement. Other industry recognized methods can also be used. JEDEC Standard No. 22-A122A Page 6 Test Method A122A (Revision of A122) 4 Procedure (contd) 4.4 Test Conditions Table 2 lists several typical test conditions. Boundary values are +5 C and -10 C for Tcycle(min)and + 10 C and -5 C for Tcycle(max). Other test conditions are acceptable based on product requirements and these conditions should be noted in the test summary. Table 2