EN 61988-3-2-2009 en Plasma display panels - Part 3-2 Interface - Electrical interface《等离子体显示屏 第3-2部分 接口 电气接口》.pdf

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1、raising standards worldwideNO COPYING WITHOUT BSI PERMISSION EXCEPT AS PERMITTED BY COPYRIGHT LAWBSI Standards PublicationPlasma display panels Part 3-2: Interface Electrical interfaceBS EN 61988-3-2:2009National forewordThis British Standard is the UK implementation of EN 61988-3-2:2009. It isident

2、ical to IEC 61988-3-2:2009.The UK participation in its preparation was entrusted to Technical CommitteeEPL/47, Semiconductors.A list of organizations represented on this committee can be obtained onrequest to its secretary.This publication does not purport to include all the necessary provisions of

3、acontract. Users are responsible for its correct application. BSI 2010ISBN 978 0 580 60350 1ICS 31.260Compliance with a British Standard cannot confer immunity fromlegal obligations.This British Standard was published under the authority of the StandardsPolicy and Strategy Committee on 31 January 20

4、10Amendments issued since publicationAmd. No. Date Text affectedBRITISH STANDARDBS EN 61988-3-2:2009EUROPEAN STANDARD EN 61988-3-2 NORME EUROPENNE EUROPISCHE NORM November 2009 CENELEC European Committee for Electrotechnical Standardization Comit Europen de Normalisation Electrotechnique Europisches

5、 Komitee fr Elektrotechnische Normung Central Secretariat: Avenue Marnix 17, B - 1000 Brussels 2009 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members. Ref. No. EN 61988-3-2:2009 E ICS 31.260 English version Plasma display panels - Part 3-2: Inte

6、rface - Electrical interface (IEC 61988-3-2:2009) Panneaux daffichage plasma - Partie 3-2: Interface - Interface lectrique (CEI 61988-3-2:2009) Plasmabildschirme - Teil 3-2: Schnittstelle - Elektrische Schnittstelle (IEC 61988-3-2:2009) This European Standard was approved by CENELEC on 2009-09-01. C

7、ENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration. Up-to-date lists and bibliographical references concerning such national standards may be obtained o

8、n application to the Central Secretariat or to any CENELEC member. This European Standard exists in three official versions (English, French, German). A version in any other language made by translation under the responsibility of a CENELEC member into its own language and notified to the Central Se

9、cretariat has the same status as the official versions. CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Cyprus, the Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta,

10、the Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia, Spain, Sweden, Switzerland and the United Kingdom. BS EN 61988-3-2:2009EN 61988-3-2:2009 - 2 - Foreword The text of document 110/181/FDIS, future edition 1 of IEC 61988-3-2, prepared by IEC TC 110, Flat panel display devices, wa

11、s submitted to the IEC-CENELEC parallel vote and was approved by CENELEC as EN 61988-3-2 on 2009-09-01. The following dates were fixed: latest date by which the EN has to be implemented at national level by publication of an identical national standard or by endorsement (dop) 2010-06-01 latest date

12、by which the national standards conflicting with the EN have to be withdrawn (dow) 2012-09-01 Annex ZA has been added by CENELEC. _ Endorsement notice The text of the International Standard IEC 61988-3-2:2009 was approved by CENELEC as a European Standard without any modification. In the official ve

13、rsion, for Bibliography, the following notes have to be added for the standards indicated: IEC 60068-1 NOTE Harmonized as EN 60068-1:1994 (not modified). IEC 60107-1 NOTE Harmonized as EN 60107-1:1997 (not modified). _ BS EN 61988-3-2:2009- 3 - EN 61988-3-2:2009 Annex ZA (normative) Normative refere

14、nces to international publications with their corresponding European publications The following referenced documents are indispensable for the application of this document. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document (in

15、cluding any amendments) applies. NOTE When an international publication has been modified by common modifications, indicated by (mod), the relevant EN/HD applies. Publication Year Title EN/HD Year IEC 61988-1 -1)Plasma display panels - Part 1: Terminology and letter symbols EN 61988-1 20032)IEC 6198

16、8-2-1 -1)Plasma display panels - Part 2-1: Measuring methods - Optical EN 61988-2-1 20022)IEC 61988-2-2 -1)Plasma display panels - Part 2-2: Measuring methods - Optoelectrical EN 61988-2-2 20032)ANSI TIA/ EIA-644-A -1)Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface

17、Circuits- - JEIDA-59 1999 Digital Interface Standards for Monitor - - 1)Undated reference. 2)Valid edition at date of issue. BS EN 61988-3-2:2009 2 61988-3-2 IEC:2009 CONTENTS 1 Scope.5 2 Normative references .5 3 Terms, definitions and abbreviations 5 3.1 Terms and definitions 5 3.2 Abbreviations 5

18、 4 Electrical interface requirements 6 5 Electrical interface of digital signal .6 5.1 Basic configuration6 5.2 Interface input signal definition7 5.3 Pin assignment9 5.4 Input signal timing .10 5.5 Power requirement 10 Annex A (informative) LVDS, TTL and TMDS.11 Bibliography24 Figure 1 Block diagra

19、m of an example interface of data signal .7 Figure A.1 Interface configuration 11 Figure A.2 Timing chart for resolution 1024 x 768 14 Figure A.3 Logic power and LVDS signals sequencing diagram .15 Figure A.4 Data enable timing parameters .16 Figure A.5 Interface configuration 17 Figure A.6 Interfac

20、e configuration 20 Table 1 Example of interface signal function 8 Table 2 Example of connector pin assignments9 Table A.1 Signal definition and function .12 Table A.2 Connector pin assignment13 Table A.3 Input signal timing specification for resolution 1024x76815 Table A.4 Input signal specification

21、s 18 Table A.5 Connector pin assignments19 Table A.6 Input signal specifications 21 Table A.7 Example of pin assignment of connector 21 Table A.8 Limiting values (Absolute maximum rating system) .22 Table A.9 Electrical characteristics 23 BS EN 61988-3-2:200961988-3-2 IEC:2009 5 PLASMA DISPLAY PANEL

22、S Part 3-2: Interface Electrical interface 1 Scope This part of IEC 61988 defines the electrical interface of digital video data signals, synchronization signals and functional signals between the image processing board of the PDP set and the control board of the PDP module, and defines the descript

23、ion of the pin assignment of the connectors. 2 Normative references The following referenced documents are indispensable for the application of this document. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document (including any am

24、endments) applies. IEC 61988-1, Plasma display panels Part 1: Terminology and letter symbols IEC 61988-2-1, Plasma display panels Part 2-1: Measuring methods Optical IEC 61988-2-2, Plasma display panels Part 2-2: Measuring methods Optoelectrical TIA/EIA-644A, Electrical characteristics of low voltag

25、e differential signaling (LVDS) interface circuits JEIDA-59-1999, Digital interface standards for monitor (only available in English) 3 Terms, definitions and abbreviations 3.1 Terms and definitions For the purposes of this document, the terms and definitions given in IEC 61988-1, IEC 60068-1 and IE

26、C 60107-1 as well as the following apply. 3.1.1 image processing board circuit board including A/D converter, scaler and video decoder, deinterlacing for image signal from input device such as TV-tuner, PC, DVD, etc. 3.2 Abbreviations NOTE The following are acronyms for reference. TTL Transistor-tra

27、nsistor logic LVDS Low voltage differential signalling TMDS Transition minimized differential signalling HS Horizontal synchronization VS Vertical synchronization DE Data enable DCLK Data clock APC Auto power control BS EN 61988-3-2:2009 6 61988-3-2 IEC:2009 4 Electrical interface requirements The e

28、lectrical interface of PDP module is a power sequence and a digital interface of PDP module. The power sequence of PDP module is power on- and off-sequence of all power supplies in and to PDP module. The power on- and off-sequence of PDP module shall be fully described in each relevant specification

29、. The digital signal interface is either an LVDS, a TTL or a TMDS interface, whose signal encodes the digital video data and function control signals. Function control signal, which is the additional signal, except digital video signal, to control the functions such as APC, shall be fully described

30、in each detail specification. The interface configuration, input signal definition, pin assignment, input signal timing and power requirement shall be described in each detail specification. 5 Electrical interface of digital signal 5.1 Basic configuration The basic configuration of electrical interf

31、ace of digital signal is shown in Figure 1 as one of examples. Examples of LVDS, TTL and TMDS are explained in Annex A. BS EN 61988-3-2:200961988-3-2 IEC:2009 7 VS Function control signals HS DE DCLK B0 Bn1G0 Gn1R0 Rn1VS HS DE DCLK B0 Bn1G0 Gn1R0 Rn1LVDS TTL TMDS Electrical interface signal (Display

32、 data signal and control signal) Image processing board PDP module Function control signals IEC 1348/09 NOTE 1 The image processing board includes A/D converter, scaler and video decoder for image signal from input device such as TV-tuner, PC, DVD, etc. NOTE 2 Ri, Gi and Bi: ith bit data for n-bit d

33、igital video signal of red, green and blue, respectively (i=0 to n-1). Figure 1 Block diagram of an example interface of data signal 5.2 Interface input signal definition The example of interface signal definition and function is as follows in Table 1. BS EN 61988-3-2:2009 8 61988-3-2 IEC:2009 Table

34、 1 Example of interface signal function Symbol I/O Function Description Rx IN0+ (or RA+) I LVDS differential data (+) Rx IN0 - (or RA-) I Display data signal: R0, R1, R2, R3, R4, R5, G0LVDS differential data (-) Rx IN1+ (or RB+) I LVDS differential data (+) Rx IN1 - (or RB-) I Display data signal: G

35、1, G2, G3, G4, G5, B0, B1LVDS differential data (-) Rx IN2+ (or RC+) I LVDS differential data (+) Rx IN2 - (or RC-) I Display data signal: B2, B3, B4, B5, HS, VS, DE LVDS differential data (-) Rx IN3+ (or RD+) I LVDS differential data (+) Rx IN3 - (or RD-) I Display data signal and control signal: R

36、6, R7, G6, G7, B6, B7, RES LVDS differential data (-) Rx IN4+ (or RE+) I LVDS differential data (+) Rx IN4- (or RE-) I Display data signal and control signal: B8, B9, G8, G9, R8, R9, RES LVDS differential data (-) Rx CLKIN+(or CLK+) I LVDS differential clock (+) Rx CLKIN-(or CLK-) I Data clock signa

37、l: DCLK LVDS differential clock (-) NOTE This example shows the case of LVDS with 10-bit video signal. BS EN 61988-3-2:200961988-3-2 IEC:2009 9 5.3 Pin assignment The pin assignments should be given in the form of Table 2. Table 2 Example of connector pin assignments Pin no Pin name 1 GND 2 GND 3 Rx

38、 IN0- 4 Rx IN0+ 5 GND 6 GND 7 Rx IN1- 8 Rx IN1+ 9 GND 10 GND 11 Rx IN2- 12 Rx IN2+ 13 GND 14 GND 15 Rx CLKIN- 16 Rx CLKIN+ 17 GND 18 GND 19 Rx IN3- 20 Rx IN3+ 21 GND 22 GND 23 GND 24 GND 25 RX IN4- 26 RX IN4+ 27 GND 28 GND 29 GND 30 GND 31 GND BS EN 61988-3-2:2009 10 61988-3-2 IEC:2009 5.4 Input sig

39、nal timing Timing of the interface signals of the PDP module shall be fully described. An example is given in A.1. 5.5 Power requirement Power requirements, and power on sequence when needed, shall be fully described. An example is given in A.1.1. BS EN 61988-3-2:200961988-3-2 IEC:2009 11 Annex A (i

40、nformative) LVDS, TTL and TMDS A.1 Video A.1.1 LVDS A.1.1.1 Basic configuration Figure A.1 shows an example of interface configuration of LVDS. PDP module Image processing board LVDS receiver (Serial / Parallel) LVDS transmitter (Parallel / Serial) Function control signals CLK m bitsFunction control

41、 signals VS HS DE DCLK B0 Bn1G0 Gn1R0 Rn1B0 Bn1G0 Gn1R0 Rn1VS HS DE DCLK CLK+ Tx/Rx4Tx/Rx4+Tx/Rx3Tx/Rx3+Tx/Rx2Tx/Rx2+Tx/Rx1Tx/Rx1+Tx/Rx0Tx/Rx0+IEC 1349/09 Figure A.1 Interface configuration BS EN 61988-3-2:2009 12 61988-3-2 IEC:2009 A.1.1.2 Interface input signal specification The input signal (disp

42、lay data signal and control signal) is converted from parallel data to serial data with the LVDS transmitter and further converted into six sets of differential signals before input to the PDP module. The LVDS signal definition and function is as follows in Table A.1. Table A.1 Signal definition and

43、 function Symbol I/O Function Description Rx IN0+ (or RA+) I LVDS differential data (+) Rx IN0- (or RA-) I Display data signal: R0, R1, R2, R3, R4, R5, G0LVDS differential data (-) Rx IN1+ (or RB+) I LVDS differential data (+) Rx IN1- (or RB-) I Display data signal: G1, G2, G3, G4, G5, B0, B1LVDS di

44、fferential data (-) Rx IN2+ (or RC+) I LVDS differential data (+) Rx IN2- (or RC-) I Display data signal: B2, B3, B4, B5, HS, VS, DE LVDS differential data (-) Rx IN3+ (or RD+) I LVDS differential data (+) Rx IN3- (or RD-) I Display data signal and control signal: R6, R7, G6, G7, B6, B7, RES LVDS di

45、fferential data (-) Rx IN4+ (or RE+) I LVDS differential data (+) Rx IN4- (or RE-) I Display data signal and control signal: B8, B9, G8, G9, R8, R9, RES LVDS differential data (-) Rx CLKIN+ (or DCLK+) I LVDS differential clock (+) Rx CLKIN- (or DCLK-) I Data clock signal: DCLK LVDS differential cloc

46、k (-) BS EN 61988-3-2:200961988-3-2 IEC:2009 13 A.1.1.3 Pin assignment The pin names may be given in the form of Table A.2. Table A.2 Connector pin assignment Pin no Pin name 1 GND 2 GND 3 Rx IN0- 4 Rx IN0+ 5 GND 6 GND 7 Rx IN1- 8 Rx IN1+ 9 GND 10 GND 11 Rx IN2- 12 Rx IN2+ 13 GND 14 GND 15 Rx CLKIN-

47、 16 Rx CLKIN+17 GND 18 GND 19 Rx IN3- 20 Rx IN3+ 21 GND 22 GND 23 GND 24 GND 25 RX IN4- 26 RX IN4+ 27 GND 28 GND 29 GND 30 GND 31 GND BS EN 61988-3-2:2009 14 61988-3-2 IEC:2009 A.1.1.4 Input signal timing chart Figure A.2 is an example of input signal timing chart. tvsyncVS HS thsyncShaded area : In

48、valid data DE DCLK thbptdclk(Period of valid data) 1 tvbp768 Line number HS Data D1 D2 D3 D1 0241 2 3 1 024 4 thfpthw2 3 - - 767 768 1 2 3 - - 767 768 1 2 3 - - - tvfptvwIEC 1350/09 Figure A.2 Timing chart for resolution 1 024 x 768 BS EN 61988-3-2:200961988-3-2 IEC:2009 15 A.1.1.5 Input signal timi

49、ng specification Table A.3 is an example of input signal timing specification. Table A.3 Input signal timing specification for resolution 1024 x 768 No Symbol Typical value Unit Remark 1 tvsync16,667 ms 60 Hz, 806 lines 2 tvw0,12 ms 6 lines 3 tvbp0,60 ms 29 lines4 tvfp0,06 ms 3 lines 5 thsync20,667 s 1 344 dots 6 thw2,09 s 136 dots 7 thbp2,46 s 160 dots 8 th