DLA SMD-5962-96901 REV D-2004 MICROCIRCUIT HYBRID MEMORY 512K X 16-BIT SRAM AND FLASH EPROM《512K X 16-BIT静态存储器和可擦可编程只读存储器混合记忆微电路》.pdf

《DLA SMD-5962-96901 REV D-2004 MICROCIRCUIT HYBRID MEMORY 512K X 16-BIT SRAM AND FLASH EPROM《512K X 16-BIT静态存储器和可擦可编程只读存储器混合记忆微电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-96901 REV D-2004 MICROCIRCUIT HYBRID MEMORY 512K X 16-BIT SRAM AND FLASH EPROM《512K X 16-BIT静态存储器和可擦可编程只读存储器混合记忆微电路》.pdf（24页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Table I; Changed the maximum limit for the SRAM supply current test from 260 mA to 270 mA. -sld 98-02-11 K. A. Cottongim B Table I; Changed the maximum limit for the standby current test from 35 mA to 45 mA. 98-06-26 K. A. Cottongim C Made correc

2、tions to case outline X. Updated drawing to reflect the latest requirements of MIL-PRF-38534.-sld 03-12-22 Raymond Monnin D Table I; Changed the IOLcondition from 8 mA to 6 mA for device type 02 during the VOLStest. Editorial changes throughout. -sld 04-04-29 Raymond Monnin REV SHEET REV D D D D D D

3、 D D D SHEET 15 16 17 18 19 20 21 22 23 REV STATUS REV D D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Steve L. Duncan DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Michael Jones COLUMBUS, OHIO 43216 http:/www.dscc.dla.mil A

4、PPROVED BY Kendall A. Cottongim MICROCIRCUIT, HYBRID, MEMORY, 512K x 16-BIT, SRAM AND FLASH EPROM THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 97-02-25 AMSC N/A REVISION LEVEL D SIZE A CAGE CODE 67268 5962-96901 SHEET 1 OF 23 DS

5、CC FORM 2233 APR 97 5962-E252-04 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96901 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scop

6、e. This drawing documents five product assurance classes as defined in paragraph 1.2.3 and MIL-PRF-38534. A choice of case outlines and lead finishes which are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of radiation hardness assurance levels are ref

7、lected in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 5962 - 96901 01 H M X Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 Radiat

8、ion hardness assurance (RHA) designator. RHA marked devices shall meet the MIL-PRF-38534 specified RHA levels and shall be marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type

9、 Generic number Circuit function Access time 01 WSF512K16-72Q 512K x 16-bit SRAM and 70 ns 512K x 16-bit Flash EPROM 120 ns 02 WSF512K16-39Q 512K x 16-bit SRAM and 35 ns 512K x 16-bit Flash EPROM 90 ns 1.2.3 Device class designator. This device class designator shall be a single letter identifying t

10、he product assurance level. All levels are defined by the requirements of MIL-PRF-38534 and require QML Certification as well as qualification (Class H, K, and E) or QML Listing (Class G and D). The product assurance levels are as follows: Device class Device performance documentation K Highest reli

11、ability class available. This level is intended for use in space applications. H Standard military quality class level. This level is intended for use in applications where non-space high reliability devices are required. G Reduced testing version of the standard military quality class. This level u

12、ses the Class H screening and In-Process Inspections with a possible limited temperature range, manufacturer specified incoming flow, and the manufacturer guarantees (but may not test) periodic and conformance inspections (Group A, B, C and D). E Designates devices which are based upon one of the ot

13、her classes (K, H, or G) with exception(s) taken to the requirements of that class. These exception(s) must be specified in the device acquisition document; therefore the acquisition document should be reviewed to ensure that the exception(s) taken will not adversely affect system performance. D Man

14、ufacturer specified quality class. Quality level is defined by the manufacturers internal, QML certified flow. This product may have a limited temperature range. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 596

15、2-96901 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style M See figure 1 68 Ceramic, dual c

16、avity, quad flatpack X See figure 1 66 Hex-in-line, single cavity, with standoffs 1.2.5 Lead finish. The lead finish shall be as specified in MIL-PRF-38534. 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc Input voltage range . -0.5 V dc to +7.0 V dc Power dissipati

17、on (PD). 1.43 W maximum Storage temperature range . -65C to +150C Lead temperature (soldering, 10 seconds) +300C Thermal resistance junction-to-case (JC): Case outline M. 12.8C/W Case outline X 8.7C/W Data retention (Flash) 10 years minimum Endurance (Flash). 10,000 cycles minimum 1.4 Recommended op

18、erating conditions. Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Input low voltage range (VIL) -0.5 V dc to +0.8 V dc Input high voltage range (VIH) +2.2 V dc to VCC+ 0.3 V dc Output voltage, high minimum (VOH) . +2.4 V dc Output voltage, low maximum (VOL) +0.4 V dc Case operating temperature r

19、ange (TC) -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the s

20、olicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38534 - Hybrid Microcircuits, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard for Electronic Component Case Outlines. DEPARTMENT OF DEFE

21、NSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or www.dodssp.daps.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Bu

22、ilding 4D, Philadelphia, PA 19111-5094.) 1/ Stresses above the absolute maximum ratings may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Provided by IHSNot for ResaleNo reproduction or networking permitted without lice

23、nse from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96901 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of t

24、his drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item performance requirements for device classes D, E, G, H, and K shall be in accordance w

25、ith MIL-PRF-38534. Compliance with MIL-PRF-38534 shall include the performance of all tests herein or as designated in the device manufacturers Quality Management (QM) plan or as designated for the applicable device class. The manufacturer may eliminate, modify or optimize the tests and inspections

26、herein, however the performance requirements as defined in MIL-PRF-38534 shall be met for the applicable device class. In addition, the modification in the QM plan shall not affect the form, fit, or function of the device for the applicable device class. 3.2 Design, construction, and physical dimens

27、ions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38534 and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 T

28、ruth table(s). The truth table(s) shall be as specified on figure 3. 3.2.4 Timing diagram(s). The timing diagram(s) shall be as specified on figures 4, 5, 6, 7, 8 and 9. 3.2.5 Block diagram(s). The block diagram(s) shall be as specified on figure 10. 3.2.6 Output load circuit. The output load circui

29、t shall be as specified on figure 11. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full specified operating temperature range. 3.4 Electrical test requirements. The elect

30、rical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Programming procedure. The programming procedure shall be as specified by the manufacturer and shall be available upon request. 3.6 Marking of device(s). Marking o

31、f device(s) shall be in accordance with MIL-PRF-38534. The device shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers vendor similar PIN may also be marked. 3.7 Data. In addition to the general performance requirements of MIL-PRF-38534, the manufacturer of the device de

32、scribed herein shall maintain the electrical test data (variables format) from the initial quality conformance inspection group A lot sample, for each device type listed herein. Also, the data should include a summary of all parameters manually tested, and for those which, if any, are guaranteed. Th

33、is data shall be maintained under document revision level control by the manufacturer and be made available to the preparing activity (DSCC-VA) upon request. 3.8 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to supply to this drawing. The certi

34、ficate of compliance (original copy) submitted to DSCC-VA shall affirm that the manufacturers product meets the performance requirements of MIL-PRF-38534 and herein. 3.9 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38534 shall be provided with each lot of microcirc

35、uits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96901 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrica

36、l performance characteristics. Limits Test Symbol Conditions 1/ 2/ -55C TC+125C unless otherwise specified Group A subgroups Device types Min Max Unit DC parameters. SRAM supply current ICC1SCS = VIL, OE = FCS = VIH, VCC= 5.5 V dc, f = 5 MHz1,2,3 All 270 mA Flash supply current for read only ICC2FCS

37、 = VIL, OE = SCS = VIH, VCC= 5.5 V dc, f =5 MHz 1,2,3 All 130 mA Flash supply current for program or erase ICC3FCS = VIL, OE = SCS = VIH, VCC= 5.5 V dc, f =5 MHz 1,2,3 All 150 mA Standby current ISBFCS = SCS = VIH, OE = VIH, VCC= 5.5 V dc, f =5 MHz 1,2,3 All 45 mA Input leakage current ILIVIN= VSSto

38、 VCC1,2,3 All 10 A Output leakage current ILOSCS = FCS = VIH, OE = VIH, VOUT= VSSto VCC1,2,3 All 10 A Input low voltage VIL1,2,3 All 0.8 V Input high voltage VIH 1,2,3 All 2.2 V FCS = VIH, VCC = 4.5 V, IOL= 2.1 mA 01 0.4 V SRAM output low voltage VOLSFCS = VIH, VCC = 4.5 V, IOL= 6 mA 1,2,3 02 0.4 V

39、Flash ouput low voltage VOLFSCS = VIH, VCC = 4.5 V, IOL= 12 mA 1,2,3 All 0.45 V FCS = VIH, VCC = 4.5 V, IOH= -1.0 mA 01 2.4 V SRAM output high voltage VOHSFCS = VIH, VCC = 4.5 V, IOH= -4.0 mA 1,2,3 02 2.4 V See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking per

40、mitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96901 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbol Conditions 1/ -55C TC+125C unles

41、s otherwise specified Group A subgroups Device types Min Max Unit Flash output high voltage VOHFSCS = VIH, VCC = 4.5 V, IOL= -2.5 mA 1,2,3 All 0.85 x VCCV Functional testing. Functional tests See 4.3.1c 7,8A,8B All Dynamic characterisitics. A0-A16 input 2/ OE capacitance CADCOEVIN= 0 V, f = 1.0 MHz,

42、 TA= +25C 4 All 50 pF F/S CS1-2 capacitance 2/ CCSVIN= 0 V, f = 1.0 MHz, TA= +25C 4 All 20 pF F/S WE1-2 capacitance 2/ CWEVIN= 0 V, f = 1.0 MHz, TA= +25C 4 All 20 pF S/F D0-D15 capacitance 2/ CI/OVIN= 0 V, f = 1.0 MHz, TA= +25C 4 All 20 pF SRAM read cycle AC timing characteristics. Read cycle time t

43、RCSee figure 4 9,10,11 01 02 70 35 ns Address access time tAA See figure 4 9,10,11 01 02 70 35 ns Chip select access time tACSSee figure 4 9,10,11 01 02 70 35 ns Output enable to output valid tOESee figure 4 9,10,11 01 02 35 25 ns Output hold from address change tOHSee figure 4 9,10,11 01 02 5 0 ns

44、Chip select high to output in high Z 2/ tCHZSee figure 4 9,10,11 01 02 25 15 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96901 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OH

45、IO 43216-5000 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbol Conditions 1/ -55C TC+125C unless otherwise specified Group A subgroups Device types Min Max Unit SRAM read cycle AC timing characteristics - Continued. Output

46、 enable high to output in high Z 2/ tOHZSee figure 4 9,10,11 01 02 25 15 ns Chip select to output in 2/ low Z tCLZSee figure 4 9,10,11 01 02 10 4 ns Output enable to output in low Z 2/ tOLZSee figure 4 9,10,11 01 02 5 0 ns SRAM write cycle AC timing characterisitics. Write cycle time tWCSee figures

47、5 and 6 9,10,11 01 02 70 35 ns Address setup time tASSee figures 5 and 6 9,10,11 All 0 ns Write pulse width tWPSee figures 5 and 6 9,10,11 01 02 50 25 ns Address hold time tAHSee figures 5 and 6 9,10,11 01 02 5 0 ns Data hold time tDHSee figures 5 and 6 9,10,11 All 0 ns Chip select to end of write t

48、CWSee figures 5 and 6 9,10,11 01 02 60 25 ns Address valid to end of write tAWSee figures 5 and 6 9,10,11 01 02 60 25 ns Data valid to end of write tDWSee figures 5 and 6 9,10,11 01 02 30 20 ns Output active from end of write 2/ tOWSee figure 5 9,10,11 01 02 5 0 ns Write enable to output in high Z 2/ tWHZSee figure 5 9,10,11 01 02 25 15 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAW