DLA SMD-5962-96889 REV A-2006 MICROCIRCUIT DIE MEMORY DIGITAL CMOS 4M X 1 DYNAMIC RANDOM ACCESS MEMORY (DRAM) MONOLITHIC SILICON《4M X 1动态随机存取存储器硅单片电路数字记忆微电路》.pdf

《DLA SMD-5962-96889 REV A-2006 MICROCIRCUIT DIE MEMORY DIGITAL CMOS 4M X 1 DYNAMIC RANDOM ACCESS MEMORY (DRAM) MONOLITHIC SILICON《4M X 1动态随机存取存储器硅单片电路数字记忆微电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-96889 REV A-2006 MICROCIRCUIT DIE MEMORY DIGITAL CMOS 4M X 1 DYNAMIC RANDOM ACCESS MEMORY (DRAM) MONOLITHIC SILICON《4M X 1动态随机存取存储器硅单片电路数字记忆微电路》.pdf（22页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Boilerplate update and part of five year review. tcr 06-04-05 Raymond Monnin REV SHET REV A A A A A A A SHEET 15 16 17 18 19 20 21 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Je

2、ff Bowling DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeff Bowling COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL APPROVED BY Raymond Monnin DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 96-10-15 MI

3、CROCIRCUIT DIE, MEMORY, DIGITAL, CMOS, 4M X 1 DYNAMIC RANDOM ACCESS MEMORY (DRAM), MONOLITHIC SILICON AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-96889 SHEET 1 OF 21 DSCC FORM 2233 APR 97 5962-E241-06 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license fro

4、m IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96889 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing establishes minimum requirements for microcircuit die to be supplied under the Qualified Manufacturers Li

5、st (QML) Program. QML microcircuit die meeting the requirements of MIL-PRF-38535 and the manufacturers approved QM plan for use in monolithic microcircuits, multichip modules (MCMs), hybrids, electronic modules, or devices using chip and wire designs in accordance with MIL-PRF-38534 are specified he

6、rein. Two product assurance classes consisting of military high-reliability (device class Q) and space application (device class V) are reflected in the Part or Identification Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels shall be reflected in the PIN. 1.2 PIN.

7、The PIN is as shown in the following example: 5962 - 96889 01 Q 9 X | | | | | | | | | | | | Federal RHA Device Device Die Die stock class designator type class Code details designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q

8、 and V RHA identified die shall meet the MIL-PRF-38535 specified RHA levels. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Access time 01 MT4C1004JD37M 4 MEG X 1 DRAM Die (5 V) 60

9、ns 02 MT4C1004JD37M 4 MEG X 1 DRAM Die (5 V) 70 ns 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Die detail

10、s. The die details designator shall be a unique letter which identifies the dies physical dimensions, bonding pad location(s) and related electrical function(s), interface materials, and other assembly related information for each product and variant supplied to this drawing. 1.2.4.1 Die physical di

11、mensions. Die type Figure number 01 1 02 1 1.2.4.2 Die bonding pad locations and electrical functions. Die type Figure number 01 1 02 1 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96889 DEFENSE SUPPLY CEN

12、TER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.2.4.3 Interface materials. Die type Figure number 01 1 02 1 1.2.4.4 Assembly related information. Die type Figure number 01 1 02 1 1.3 Absolute maximum ratings. 1/ Voltage on any pin relative to VSS.- 1 V to + 7

13、V Operating Temperature TAambient0C to 70C Storage temperature.-55C to +150C Power Dissipation.1 W Short circuit output current50 mA 1.4 Recommended operating conditions. Supply voltage 4.5 V to 5.5 V 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following speci

14、fication, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Sp

15、ecification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.dap

16、s.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this d

17、rawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade perform

18、ance and affect reliability. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96889 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 I

19、tem requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as desc

20、ribed herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and the manufacturers QM plan for device classes Q and V and herein. 3.2.1 Die physical dimensions. The die physical dimensions shall be as specif

21、ied in 1.2.4.1 and on figure 1. 3.2.2 Die bonding pad locations and electrical functions. The die bonding pad locations shall be as specified in 1.2.4.2 and on figure 1. 3.2.3 Interface materials. The interface materials for the die shall be as specified in 1.2.4.3 and on figure 1. 3.2.4 Assembly re

22、lated information. The assembly related information shall be as specified in 1.2.4.4 and on figure 1. 3.2.5 Truth table(s). The truth table shall be as specified on figure 2. 3.2.6 Timing waveforms. The timing waveforms shall be as specified on figure 3. 3.3 Electrical performance characteristics an

23、d post-irradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and post-irradiation parameter limits of the die are as specified in table I. 3.4 Electrical test requirements. The wafer probe test requirements shall include functional and parametric

24、 testing sufficient to make the packaged die capable of meeting the electrical performance requirements of table I. Waferprobe speed sorting is available upon request by the customer. 3.5 Marking. As a minimum, each unique lot of die, loaded in a single or multiple stack of carriers, for shipment to

25、 a customer, shall be identified with the wafer lot number, a date code, the certification mark, the manufacturers identification and the PIN specified in 1.2 herein. The certification mark shall be a “QML“ or “Q“ as required by MIL-PRF-38535. 3.6 Certificate of compliance. For device classes Q and

26、V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.4 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the ma

27、nufacturers product meets, for die classes Q and V, the requirements of MIL-PRF-38535 and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance shall be required for device classes Q and V in accordance with the applicable requirements of MIL-PRF-38535 and shall be pr

28、ovided with each lot of microcircuit die delivered to this drawing. 4. VERIFICATION 4.1 Sampling and inspection. For device classes Q and V, die sampling and inspection procedures including screening and conformance inspection shall be in accordance with the applicable requirements of MIL-PRF-38535

29、for die or as modified in the device manufacturers Quality Management (QM) plan. The modifications in the QM plan shall not affect the form, fit or function as described herein. 4.2 Qualification inspection for die classes Q and V. For die classes Q and V, qualification inspection shall be in accord

30、ance with the applicable die requirements of MIL-PRF-38535. Die inspections to be performed shall be those specified in MIL-PRF-38535 and in the manufacturers QM plan. 4.3 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and as defined in the manufacturers

31、QM plan. As a minimum it shall consist of: 4.3.1 Wafer lot acceptance for class V. Wafer lot acceptance for class V product shall use the criteria of method 5007 of MIL-STD-883 or an equivalent method approved by the qualifying activity. 4.3.2 Wafer probe. 100 percent wafer probe shall be required i

32、n accordance with 3.4 herein. 4.3.3 Internal visual. 100 percent internal visual inspection to the applicable class Q or V criteria of method 2010 of MIL-STD-883 or an alternate procedures allowed in method 5004 of MIL-STD-883 or an inspection methodology approved by the qualifying activity. Provide

33、d by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96889 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Limits T

34、est Symbol Conditions 0C TC+70C 4.5 V VCC 5.5 V unless otherwise specified Notes Device Type Min Max Unit Supply voltage VCC1/ 3/ 5/ 6/ All 4.5 5.5 V Input high voltage VIH1/ 3/ 5/ 6/ All 2.4 VCC+ 1 V Input low voltage VIL1/ 3/ 5/ 6/ All -1.0 0.8 V Input leakage current IIAny input 0 V VIN6.5 V All

35、other pins not under test = 0 V 1/ 3/ 5/ 6/ All -2 2 A Output leakage current IOZQ is disabled 0 V VOUT 5.5 V 1/ 3/ 5/ 6/ All -10 10 A Output high voltage VOHIOUT= -5 mA 1/ 3/ 5/ 6/ All 2.4 V Output low voltage VOLIOUT= 4.2 mA 1/ 3/ 5/ 6/ All 0.4 V Standby current (TTL) ICC1RAS = CAS = VIHAll 2 mA S

36、tandby current (CMOS) ICC2RAS = CAS = VCC- 0.2 V All 1 mA 01 110 Operating current (random read/write) ICC3RAS , CAS single address cycling, tRC= tRC(min) 3/ 25/ 02 100 mA 01 80 Operating current (fast page mode) ICC4RAS = VIL, CAS address cycling, tRC= tRC(min) 3/ 25/ 02 70 mA 01 110 Refresh curren

37、t RAS only ICC5RAS cycling, CAS = VIH, tRC= tRC(min) 3/ 25/ 02 100 mA 01 110 Refresh current CBR ICC6RAS , CAS , address cycling, tRC= tRC(min) 3/ 4/ 02 100 mA Input capacitance, A0-A10, D CI12/ All 5 pF Input capacitance, RAS , CAS , WE CI22/ All 7 pF Output capacitance CO2/ All 7 pF 01 110 Random

38、read or write cycle time tRC02 130 ns 01 130 Read-write cycle time tRWC02 155 ns 01 35 Fast page mode read or write cycle time tPC5/ 6/ 7/ 8/ 9/ 10/ 11/ 12/ 02 40 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STAND

39、ARD MICROCIRCUIT DRAWING SIZE A 5962-96889 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. See footnotes at end of table. Limits Test Symbol Conditions 0C TC+70C 4.5 V VCC 5.5 V unles

40、s otherwise specified Notes Device Type Min Max Unit 01 60 Fast page mode read-write cycle time tPRWC02 70 ns 01 60 Access time from RAS tRAC13/ 02 70 ns 01 15 Access time from CAS tCAC14/ 02 20 ns 01 30 Access time from column address tAA02 35 ns 01 35 Access time from CAS precharge tCPA02 40 ns 01

41、 60 10,000 RAS pulse width tRAS23/ 02 70 10,000 ns 01 60 100,000 RAS pulse width (fast page mode) tRASP23/ 02 70 100,000 ns 01 15 RAS hold time tRSH02 20 ns 01 40 RAS precharge time tRP02 50 ns 01 15 10,000 CAS pulse width tCAS02 20 10,000 ns 01 60 CAS hold time tCSH02 70 ns CAS precharge time (CBR

42、refresh) tCPNAll 10 ns CAS precharge time (fast page mode) tCP15/ All 10 ns 01 20 45 RAS to CAS delay time tRCD16/ 02 20 50 ns CAS to RAS precharge time tCRPAll 10 ns Row address setup time tASRAll 0 ns Row address hold time tRAH5/ 6/ 7/ 8/ 9/ 10/ 11/ 12/ All 10 ns Provided by IHSNot for ResaleNo re

43、production or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96889 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Limits Test Symbol Conditions 0C TC

44、+70C 4.5 V VCC 5.5 V unless otherwise specified Notes Device Type Min Max Unit 01 15 30 RAS to column address delay time tRAD17/ 02 15 35 ns Column address setup time tASCAll 0 ns 01 10 Column address hold time tCAH02 15 ns 01 45 Column address hold time referenced to RAS tAR02 50 ns 01 30 Column ad

45、dress to RAS lead time tRAL02 35 ns 01 0 Read command setup time tRCS02 0 ns 01 0 Read command hold time referenced to CAS tRCH18/ 02 0 ns 01 0 Read command hold time referenced to RAS tRRH18/ 02 0 ns 01 0 CAS to output in low Z tCLZ02 0 ns 01 3 15 Output buffer turn-off delay tOFF19/ 24/ 02 3 20 ns

46、 WE command setup time tWCSAll 0 ns 01 10 Write command hold time tWCH02 15 ns 01 45 Write command hold time referenced to RAS tWCR02 55 ns 01 10 Write command pulse width tWP02 15 ns 01 15 Write command to RAS lead time tRWL02 20 ns 01 15 Write command to CAS lead time tCWL5/ 6/ 7/ 8/ 9/ 10/ 11/ 12

47、/ 02 20 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96889 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 8 DSCC FORM 2234 APR 97 TABLE I.

48、 Electrical performance characteristics - continued. Limits Test Symbol Conditions 0C TC+70C 4.5 V VCC 5.5 V unless otherwise specified Notes Device Type Min Max Unit Data-in setup time tDS21/ All 0 ns 01 10 Data-in hold time tDH21/ 02 15 ns 01 45 Data-in hold time referenced to RAS tDHR02 55 ns 01 60 RAS to WE delay time tRWD20/ 02 70 ns 01 30 Column address to WE delay time tAWD20/ 02 35 ns 01 15 CAS to WE delay time tCWD20/ 02 20 ns Transition time (r