DLA SMD-5962-94614 REV F-2012 MICROCIRCUIT HYBRID MEMORY DIGITAL 32K x 32-BIT ELECTRICALLY ERASABLE AND PROGRAMMABLE READ ONLY MEMORY.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED C Added case outline Z. Corrected the true dimensioning table feature for case outlines U, X, and Y. -sld 98-08-13 K. A. Cottongim D Added case outline 9. Added vendor cage 0EU86 for device types 01 through 03 in the Standard Microcircuit Drawing S

2、ource Approval Bulletin. -sld 00-04-19 Raymond Monnin E Added case outline B. Added note to paragraph 1.2.4. -sld 03-10-20 Raymond Monnin F Updated drawing paragraphs. -sld 12-09-17 Charles F. Saffle REV SHEET REV F F F F F F F F F F F F F F F SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 REV S

3、TATUS REV F F F F F F F F F F F F F F OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Gary Zahn DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ STANDARD MICROCIRCUIT DRAWING CHECKED BY Michael C. Jones THIS DRAWING IS AVAILABLE FOR USE BY ALL

4、DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE APPROVED BY Kendall A. Cottongim MICROCIRCUIT, HYBRID, MEMORY, DIGITAL, 32K x 32-BIT, ELECTRICALLY ERASABLE AND PROGRAMMABLE READ ONLY MEMORY DRAWING APPROVAL DATE 94-08-26 AMSC N/A REVISION LEVEL F SIZE A CAGE CODE 67268 5962-94614 SHEET 1 OF 29

5、 DSCC FORM 2233 APR 97 5962-E472-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94614 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. Thi

6、s drawing documents five product assurance classes as defined in paragraph 1.2.3 and MIL-PRF-38534. A choice of case outlines and lead finishes which are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of radiation hardness assurance levels are reflected

7、 in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 5962 - 94614 01 H M X Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 Radiation ha

8、rdness assurance (RHA) designator. RHA marked devices shall meet the MIL-PRF-38534 specified RHA levels and shall be marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Gener

9、ic number Circuit function Access time 01 E32K32-150 EEPROM, 32K x 32-bit 150 ns 02 E32K32-120 EEPROM, 32K x 32-bit 120 ns 03 E32K32-90 EEPROM, 32K x 32-bit 90 ns 1.2.3 Device class designator. This device class designator shall be a single letter identifying the product assurance level. All levels

10、are defined by the requirements of MIL-PRF-38534 and require QML Certification as well as qualification (Class H, K, and E) or QML Listing (Class G and D). The product assurance levels are as follows: Device class Device performance documentation K Highest reliability class available. This level is

11、intended for use in space applications. H Standard military quality class level. This level is intended for use in applications where non-space high reliability devices are required. G Reduced testing version of the standard military quality class. This level uses the Class H screening and In-Proces

12、s Inspections with a possible limited temperature range, manufacturer specified incoming flow, and the manufacturer guarantees (but may not test) periodic and conformance inspections (Group A, B, C and D). E Designates devices which are based upon one of the other classes (K, H, or G) with exception

13、(s) taken to the requirements of that class. These exception(s) must be specified in the device acquisition document; therefore the acquisition document should be reviewed to ensure that the exception(s) taken will not adversely affect system performance. D Manufacturer specified quality class. Qual

14、ity level is defined by the manufacturers internal, QML certified flow. This product may have a limited temperature range. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94614 DLA LAND AND MARITIME COLUMBUS,

15、 OHIO 43218-3990 REVISION LEVEL F SHEET 3 DSCC FORM 2234 APR 97 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style B See figure 1 68 Co-fired ceramic, single cavity, quad flatpack M See figure 1 6

16、8 Ceramic, dual cavity, quad flatpack U See figure 1 66 1.075“, hex-in-line, single cavity, with standoffs X See figure 1 66 Hex-in-line, single cavity, with standoffs Y 1/ See figure 1 66 Hex-in-line, single cavity, without standoffs Z See figure 1 68 Co-fired ceramic, single cavity, ultra low prof

17、ile, quad flatpack 9 2/ See figure 1 68 Co-fired ceramic, single cavity, quad flatpack 1.2.5 Lead finish. The lead finish shall be as specified in MIL-PRF-38534. 1.3 Absolute maximum ratings. 3/ Supply voltage range (VCC) . -0.6 V dc to +6.25 V dc Input voltage range -0.6 V dc to +6.25 V dc Power di

18、ssipation (PD) . 1.5 W Storage temperature range -65 C to +150 C Lead temperature (soldering, 10 seconds) +300 C Thermal resistance junction-to-case (qJC): Case outlines M and Z 11.3 C/W Case outlines U, X, and Y 2.8 C/W Cases outline B and 9 4.57 C/W Data retention 10 years minimum Endurance . 10,0

19、00 cycles minimum 1.4 Recommended operating conditions. Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Input low voltage range (VIL) -0.5 V dc to +0.8 V dc Input high voltage range (VIH) +2.0 V dc to VCC+ 0.3 V dc Output voltage, High minimum (VOH) . +2.4 V dc Output voltage, low maximum (VOL) .

20、+0.45 V dc Case operating temperature range (TC) . -55 C to +125 C 1/ The case outline Y is inactive for new design. 2/ Due to the short leads of case outline 9, caution should be taken if the system application is to be used where extreme thermal transitions can occur. 3/ Stresses above the absolut

21、e maximum ratings may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94614 DLA L

22、AND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise

23、 specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATIONS MIL-PRF-38534 - Hybrid Microcircuits, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface

24、Standard for Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Doc

25、ument Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable l

26、aws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item performance requirements for device classes D, E, G, H, and K shall be in accordance with MIL-PRF-38534. Compliance with MIL-PRF-38534 shall include the performance of all te

27、sts herein or as designated in the device manufacturers Quality Management (QM) plan or as designated for the applicable device class. The manufacturer may eliminate, modify, or optimize the tests and inspections herein, however, the performance requirements as defined in MIL-PRF-38534 shall be met

28、for the applicable device class. In addition, the modification in the QM plan shall not affect the form, fit, or function of the device for the applicable device class. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-P

29、RF-38534 and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 3. 3.2.4 Timing diag

30、ram(s). The timing diagram(s) shall be as specified on figure 4, 5, 6, and 7. 3.2.5 Block diagram. The block diagram shall be as specified on figure 8 . 3.2.6 Output test circuit. The output test circuit shall be as specified on figure 9 . Provided by IHSNot for ResaleNo reproduction or networking p

31、ermitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94614 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 5 DSCC FORM 2234 APR 97 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristi

32、cs are as specified in table I and shall apply over the full specified operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Programming procedur

33、e. The programming procedure shall be as specified by the manufacturer and shall be available upon request. 3.6 Marking of Device(s). Marking of device(s) shall be in accordance with MIL-PRF-38534. The device shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers vendor si

34、milar PIN may also be marked. 3.7 Data. In addition to the general performance requirements of MIL-PRF-38534, the manufacturer of the device described herein shall maintain the electrical test data (variables format) from the initial quality conformance inspection group A lot sample, for each device

35、 type listed herein. Also, the data should include a summary of all parameters manually tested, and for those which, if any, are guaranteed. This data shall be maintained under document revision level control by the manufacturer and be made available to the preparing activity (DLA Land and Maritime

36、-VA) upon request. 3.8 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to supply to this drawing. The certificate of compliance (original copy) submitted to DLA Land and Maritime -VA shall affirm that the manufacturers product meets the performan

37、ce requirements of MIL-PRF-38534 and herein. 3.9 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38534 shall be provided with each lot of microcircuits delivered to this drawing. 3.10 Endurance. A reprogrammability test shall be completed as part of the vendors reliab

38、ility monitors. This reprogrammability test shall be done for the initial characterization and after any design process changes which may affect the reprogrammability of the device. The methods and procedures may be vendor specific, but shall guarantee the number of program/erase cycles listed in se

39、ction 1.3 herein over the full military temperature range. The vendors procedure shall be kept under document control and shall be made available upon request of the acquiring or preparing activity. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STA

40、NDARD MICROCIRCUIT DRAWING SIZE A 5962-94614 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55 C TC +125 C +4.5 V dc VCC +5.5 V dc unless otherwise specified Group A subgroups

41、Device type Limits Unit Min Max DC Parameters Supply current ICCCS = VIL, OE = WE = VIH, IOUT= 0 mA, VCC= 5.5 V dc, A0 through A14 and D0 through D31 change at 5 MHz CMOS levels. 1, 2, 3 01 02 03 150 200 250 mA Standby current ISBCS = OE = VIH, IOUT= 0 mA, VCC= 5.5 V dc, A0 through A14 and D0 throug

42、h D31 change at 5 MHz CMOS levels. 1, 2, 3 All 2.5 mA Input leakage current ILIVIN= VSSor VCC1, 2, 3 All 10 mA Output leakage current ILOVOUT= VSSor VCC, CS = VIH1, 2, 3 All 10 mA Output low voltage VOLIOL= 2.1 mA, VCC= +4.5 V 1, 2, 3 All 0.45 V Output high voltage VOHIOH= -400 mA, VCC= +4.5 V 1, 2,

43、 3 All 2.4 V Functional testing Functional tests See 4.3.1c 7, 8A, 8B Dynamic characteristics A0 - A14 2/ OE capacitance CAD COEVIN= 0 V, f = 1.0 MHz, TA= +25 C 4 All 50 pF CS1-4 capacitance 2/ CCSVIN= 0 V, f = 1.0 MHz, TA= +25 C 4 All 20 pF WE1-4 capacitance 2/ CWEVIN= 0 V, f = 1.0 MHz, TA= +25 C 4

44、 All 20 pF I/O0-I/O31 capacitance 2/ CI/OVI/O= 0 V, f = 1.0 MHz, TA= +25 C 4 All 20 pF See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94614 DLA LAND AND MARITIME COLUMBUS, OHIO

45、 43218-3990 REVISION LEVEL F SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55 C TC +125 C +4.5 V dc VCC +5.5 V dc unless otherwise specified Group A subgroups Device type Limits Unit Min Max Read cycle AC timing characteristics

46、Read cycle time tRCSee figure 4 9,10,11 01 02 03 150 120 90 ns Address access time tACCSee figure 4 9, 10, 11 01 02 03 150 120 90 ns Chip select access time tACSSee figure 4 9, 10, 11 01 02 03 150 120 90 ns Output hold from address change OE or CS tOHSee figure 4 9, 10, 11 All 0 ns Output enable to

47、output valid tOE See figure 4 9, 10, 11 01 02 03 70 60 50 ns Chip select or Output enable to Output high Z 2/ tDFSee figure 4 9, 10, 11 01 02 03 70 60 50 ns Byte write AC timing characteristics Address setup time tASSee figure 5 9, 10, 11 All 0 ns Write pulse width tWPSee figure 5 9, 10, 11 01 ,02 1

48、50 ns 03 100 Chip select setup time tCSSee figure 5 9, 10, 11 All 0 ns Address hold time tAHSee figure 5 9, 10, 11 01, 02 100 ns 03 50 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94614 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics -