DLA SMD-5962-91594 REV A-2012 MICROCIRCUIT MEMORY DIGITAL BICMOS 8K x 8 STATIC RANDOM ACCESS MEMORY (SRAM) MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Updated body of drawing to reflect current requirements. - glg 12-04-20 Charles F. Saffle THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV A A A A A SHEET 15 16 17 18 19 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2

2、3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Jeff Bowling DLA LAND AND MARITIME STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeff Bowling COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY All DEPARTMENTS APPROVED BY Michael. A. Frye MICROCIRCUIT, MEMOR

3、Y, DIGITAL, BICMOS, 8K x 8 STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 94-06-28 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-91594 SHEET 1 OF 19 DSCC FORM 2233 APR 97 5962-E312-12 Provided by IHSNot for ResaleNo repr

4、oduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91594 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of hig

5、h reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 Part

6、 or Identifying Number (PIN). The complete PIN shall be as shown in the following example: 5962 - 91594 01 Q X A | | | | | | | | | | | | | | | | | | Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2

7、.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked

8、with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) shall identify the circuit function as follows: Device type Generic number Circuit Access time 01 7B185 8K X 8 SRAM 15 ns 02 7B185 8K X 8 SRAM 12 ns 03 7B185 8K X 8 SRAM 10 ns 1.2.3 D

9、evice class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with

10、MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835, and as follows: Outline letter Descriptive designator Terminals Package style Y CQCC4-N28 24 Rectangular leadless chip carrier Z CDIP3-

11、T28 or GDIP4-T28 24 Dual in-line T GDFP2-F28 28 Flat pack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91594 DLA LAND AND MA

12、RITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage range to ground potential (VCC) -0.5 V dc to +7.0 V dc DC output current 20 mA Maximum power dissipation 0.853 W Lead temperature (soldering, 10 seconds) +260C Thermal resi

13、stance, junction-to-case (JC): See MIL-STD-1835 Junction temperature (TJ) . +175C Storage temperature range (TSTG) -65C to +150C Temperature under bias -55C to +125C 1.4 Recommended operating conditions. Supply voltage range (VCC) +4.5 V dc minimum to +5.5 V dc maximum Ground voltage (GND) . 0 V dc

14、Input high voltage (VIH) 2.2 V dc to VCCVdc Input low voltage (VIL) -0.5 V dc to 0.8 V dc 3/ Case operating temperature range (TC) . -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this

15、 drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-S

16、TD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at

17、https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified,

18、the issues of the documents are the issues of the documents cited in the solicitation. JEDEC INTERNATIONAL (JEDEC) JEDEC Standard No. 78 - IC Latch-Up Test. (Applications for copies should be addressed to JEDEC Solid State Technology Association, 3103 North 10thStreet, Suite 240-S, Arlington, VA 222

19、01-2107; http:/www.jedec.org.) _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ VILnegative undershoots of -3.0 V dc are allowed with a pulse width VIH, IOUT= 0 mA, f

20、= fMAX3/ 1, 2, 3 01 50 mA 02 55 03 60 Input capacitance 4/ CINVCC = 5.0 V, TA = +25C, f = 1 MHz (see 4.4.1e) 4 All 10 pF Output capacitance 4/ COUTVCC = 5.0 VTA = +25C, f = 1 MHz (see 4.4.1e) 4 All 10 pF Functional tests see 4.4.1c 7,8A, 8B All Read cycle time tAVAVFor timing waveforms, see figure 4

21、. 9, 10, 11 01 15 ns 02 12 03 10 Address access time tAVQV9, 10, 11 01 15 ns 02 12 03 10 Chip enable access time 5/ tELQV9, 10, 11 01 15 ns 02 12 03 10 Output hold from address change tAVQX9, 10, 11 All 3 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking pe

22、rmitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91594 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions 1/ -55C TC+125C 4.5 V VCC 5.5 V Grou

23、p A subgroups Device types Limits Unit unless otherwise specified Min Max Chip enable to output active 4/ 5/ tELQXFor timing waveforms, see figure 4. 9, 10, 11 01 3 ns 02,03 2 Chip disable to output inactive 4/ 5/ tEHQZ9, 10, 11 01 7 ns 02 6 03 5 Output enable to output valid 4/ 5/ 6/ tOLQV9, 10, 11

24、 01 8 ns 02 6 03 5 Output enable to output active 4/ tOLQX9, 10, 11 All 2 ns Output disable to output inactive 4/ 6/ tOHQZ9, 10, 11 01 7 ns 02 6 03 5 Write cycle time tAVAV9, 10, 11 01 15 ns 02 12 03 10 Chip enable to write end 5/ tELWH tELEH tEHWH tEHEL 9, 10, 11 01 10 ns 02,03 8 Address setup to e

25、nd of write 5/ tAVWH tAVEL 9, 10, 11 01 10 ns 02,03 8 Address setup to write start 5/ tAVWL tAVEH 9, 10, 11 All 0 ns Write recovery time 5/ tWHAX tELAX 9, 10, 11 All 0 ns Write enable pulse width tWLWH 9, 10, 11 01 10 ns 02,03 8 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduc

26、tion or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91594 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions 1/ -55C TC+125C

27、 4.5 V VCC 5.5 V Group A subgroups Device types Limits Unit unless otherwise specified Min Max Data setup to write end 5/ tDVWH tDVEL For timing waveforms, see figure 4. 9, 10, 11 01 7 ns 02 6 03 5 Data hold from write end 5/ tWHDX tELDX 9, 10, 11 All 0 ns Write enable high to output active 4/ tWHQX

28、9, 10, 11 All 2 ns Write enable low to output inactive 4/ 5/ tWLQZ tEHQZ9, 10, 11 01 7 ns 02 6 03 5 1/ AC tests are performed with input rise and fall times of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 V to 3.0 V, and the output load in figure 4, circuit A. 2/ These are

29、 absolute values with respect to device ground and all overshoots and undershoots due to system or tester noise are included. 3/ At f = fMAX, address and data inputs are cycling at the maximum frequency of 1/tAVAV. 4/ Tested initially and after any design or process changes that affect that paramete

30、r, and therefore shall be guaranteed to the limits specified in table I. 5/ The parameters which refer to the transition of CE1 or CE2reference the transition of CE1or the opposite transition of CE2. 6/ Transition is measured at steady state-high level -200 mV or steady state low level +200 mV on th

31、e output from the 1.5 V level on the input, CL= 5 pF (including scope and jig). See figure 3, circuit B. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91594 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 R

32、EVISION LEVEL A SHEET 8 DSCC FORM 2234 APR 97 Device types All Case outlines Z, T Y Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NC A A A A A A A A A I/O I/O I/O GND I/O I/O I/O I/O I/O CE1A OEA A A CE2WE VCCA A A NC A A A A A A I/O I/O I

33、/O GND I/O I/O I/O I/O I/O CE1A OEA A A CE2WE VCCNC = no connection FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91594 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISI

34、ON LEVEL A SHEET 9 DSCC FORM 2234 APR 97 CE1 CE2WEOE Inputs/Outputs Mode H X L L L X L H H H X X H L H X X L X H High Z High Z Data out Data in High Z Deselect/Powerdown Deselect Read Write Deselect FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without l

35、icense from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91594 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 10 DSCC FORM 2234 APR 97 Note: Including scope and jig (minimum values). AC test conditions Input pulse levels Input rise and fall times Input timing reference l

36、evels Output reference levels GND to 3.0 V 3 ns 1.5 V 1.5 V FIGURE 3. Output load circuit and test conditions. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91594 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-

37、3990 REVISION LEVEL A SHEET 11 DSCC FORM 2234 APR 97 Notes: 1. Device is continually selected. OE , CE1= VIL, CE2= VIH. 2. WEis held high during read cycles. 3. Address valid prior to or coincident with CE1transition low or CE2transition low. FIGURE 4. Timing waveform diagram. Provided by IHSNot for

38、 ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91594 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 12 DSCC FORM 2234 APR 97 FIGURE 4. Timing waveform diagrams - continued. Provided by IHSNot for ResaleNo

39、reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91594 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 13 DSCC FORM 2234 APR 97 Notes: 1. At any given temperature and voltage condition tWLQZis less than tWHQXfor any gi

40、ven device. 2. Data I/O is high-impedance if OE = VIH. 3. When data input is applied to the device I/O, the device output should be in the high-impedance state. 4. During this period the I/O pins are in the output state, and input signals should not be applied. 5. Address valid prior to or coinciden

41、t with CE transition low. 6. If CE goes high simultaneously with WE high, the output remains in a high-impedance state. 7. Either CE1or CE2may be used to control the write cycle. If CE1is used, CE2 should be high when WE is low. If CE2is used, CE1should be low when WE is low. FIGURE 4. Timing wavefo

42、rm diagrams - continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91594 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 14 DSCC FORM 2234 APR 97 3.8 Notification of change for de

43、vice class M. For device class M, notification to DLA Land and Maritime-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DLA Land and Maritime,

44、 DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device

45、class M devices covered by this drawing shall be in microcircuit group number 41 (see MIL-PRF-38535, appendix A). 4. VERIFICATION 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufac

46、turers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. For device classes Q and V, screening sha

47、ll be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. 4.2.1 Additi