DLA SMD-5962-91545 REV F-2007 MICROCIRCUIT MEMORY DIGITAL CMOS UV ERASEABLE PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON《CMOS数字微电路存储器 紫外光可消除可编程逻辑阵列 单片硅》.pdf

《DLA SMD-5962-91545 REV F-2007 MICROCIRCUIT MEMORY DIGITAL CMOS UV ERASEABLE PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON《CMOS数字微电路存储器 紫外光可消除可编程逻辑阵列 单片硅》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-91545 REV F-2007 MICROCIRCUIT MEMORY DIGITAL CMOS UV ERASEABLE PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON《CMOS数字微电路存储器 紫外光可消除可编程逻辑阵列 单片硅》.pdf（21页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Added low power version device, 03, with an access time of 35 ns for CAGE number 1FN41. Editorial changes throughout. 92 - 10 - 29 M. A. Frye B Changes in accordance with NOR 5962-R182-93 93 - 06 - 03 M. A. Frye C Added four devices (04 - 07). Ed

2、itorial changes throughout. 95 - 05 - 19 M. A. Frye D Changes in accordance with NOR 5962-R058-96 96 - 03 - 13 M. A. Fry E Added note to package Y. Updated boilerplate paragraphs. ksr 02 - 04 - 02 Raymond Monnin F Changed Table I Input capacitance (CI) from 8 pF to 20 pF. Changed the sample size for

3、 capacitance testing (paragraph 4.4.1e) from 15 devices to 5 devices. Corrected Figure 2 Terminal connection for case outlines X and Y for devices 04, 05, 06, and 07; to indicate that terminals 4 and 26 are GND, not NC. Added footnote 8/ to Table I select parameters. ksr 07-08-03 Robert M. Heber THE

4、 ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV F F F F F SHEET 15 16 17 18 19 REV STATUS REV F F F F F F F F F F F F F F OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.d

5、la.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles Reusing APPROVED BY Michael A. Frye DRAWING APPROVAL DATE 91 - 07 - 25 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, UV ERASEABLE PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON SIZE A CAGE CODE 67268 5962-91545 THIS DRAWING IS AVAILABLE FOR USE BY All DEP

6、ARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A REVISION LEVEL F SHEET 1 OF 19 DSCC FORM 2233 APR 97 5962-E565-06 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-91545 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMB

7、US COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M), space application (device class V). A choice of case outlines and lead finishes are avail

8、able and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 D 91545 01 Q Q A Federal RHA Device Device Case Lead stock class designator type

9、 class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RH

10、A marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) shall identify the circuit function as follows: Standby Supply Device type Generic number Circu

11、it function Access time Current 01 V2500H 38-input, 24-output and-or-logic array 35 ns 02 V2500H 38-input, 24-output and-or-logic array 25 ns 03 V2500L 38-input, 24-output and-or-logic array 35 ns 10 mA 04 V2500B 38-input, 24-output and-or-logic array 15 ns 05 V2500BL 38-input, 24-output and-or-logi

12、c array 20 ns 10 mA 06 V2500BQ 38-input, 24-output and-or-logic array 25 ns 07 V2500BQL 38-input, 24-output and-or-logic array 30 ns 5 mA 1.2.3 Device class designator. The device class designator shall be a single letter identifying the product assurance level as follows: Device class Device requir

13、ements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q, V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) shall be as designated in

14、MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style Q GDIP1-T40 or CDIP2-T40 40 Dual-in-line 1/ X CQCC1-N44 44 Square leadless chip carrier 1/ Y See figure 1 44 J - leaded chip carrier 1/ _ 1/ Lid shall be transparent to permit ultraviolet light erasure. Provid

15、ed by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-91545 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 3 DSCC FORM 2234 APR 97 1.2.5 Lead finish. The lead finish is as specified in MI

16、L-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 1.3 Absolute maximum ratings. 2/ 3/ Supply voltage range. -0.5 V dc to +7.0 V dc Input voltage range -2.0 V dc to +7.0 V dc 4/ Output voltage range applied -0.5 V dc to +7.0 V dc 4/ Output sink current 8 mA Therm

17、al resistance, junction-to-case (JC): Cases Q, X See MIL-STD-1835 Case Y 20C/W Maximum power dissipation (PD) 5/ 1.2 W Maximum junction temperature . +175C Lead temperature (soldering, 10 seconds maximum) +300C Endurance. 25 erase/write cycles (minimum) Data retention 10 years (minimum) 1.4 Recommen

18、ded operating conditions. Supply voltage range (VCC) . 4.5 V dc minimum to 5.5 V dc maximum Supply voltage (VSS) 0.0 V dc High level input voltage range (VIH) - 2.0 V dc minimum Low level input voltage range (VIL) 0.8 V dc maximum Case operating temperature range (TC) -55C to +125C 2. APPLICABLE DOC

19、UMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DE

20、FENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - Li

21、st of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia,

22、PA 19111-5094.) _ 2/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 3/ All voltages referenced to VSS. 4/ Minimum voltage is -0.6 V dc which may undershoot to -2.0 V dc for

23、pulses of less than 20 ns. Maximum output pin voltage is VCC+0.75 V dc which may overshoot to +7.0 V dc for pulses of less than 20 ns. 5/ Must withstand the added PDdue to short circuit test; e.g., IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,

24、-SIZE A 5962-91545 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 4 DSCC FORM 2234 APR 97 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified,

25、 the issues of these documents are those cited in the solicitation. AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM Standard F1192-00 - Standard Guide for the Measurement of Single Event Phenomena from Heavy Ion Irradiation of Semiconductor Devices. (Applications for copies of ASTM publicatio

26、ns should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor Drive, West Conshohocken, PA 19428-2959; http:/www.astm.org.) ELECTRONICS INDUSTRIES ASSOCIATION (EIA) JEDEC Standard EIA/JESD78 - IC Latch-Up Test. (Applications for copies should be addressed to the Electronics Industries

27、Association, 2500 Wilson Boulevard, Arlington, VA 22201; http:/www.jedec.org.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational

28、 services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3.

29、 REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535, and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit,

30、 or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-3

31、8535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and on figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Tr

32、uth table(s). The truth table(s) shall be as specified on figure 3. 3.2.3.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item drawing shall be as specified on figure 3 herein. When required in screening (see 4.2 herein), or qualification conforman

33、ce inspection groups A, B, C, or D (see 4.3 herein), the devices shall be programmed by the manufacturer prior to test in a checkerboard or similar pattern (a minimum of 50 percent of the total number of gates programmed). 3.2.3.2 Programmed devices. The truth table for programmed devices shall be a

34、s specified by an attached altered item drawing. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the fu

35、ll case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. Unless otherwise specified, the values specified in table I are the preirradiation and

36、 postirradiation values. Postirradiation electrical measurements for any RHA level are tested at, TA= +25C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-91545 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO

37、43218-3990 REVISION LEVEL F SHEET 5 DSCC FORM 2234 APR 97 3.5 Verification of erasure or programmed EPLDs. When specified, devices shall be verified as either programmed (see 4.7 herein) to the specified pattern or erased (see 4.6 herein). As a minimum, verification shall consist of performing a fun

38、ctional test (subgroup 7) to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure, and shall be removed from the lot. 3.6 Processing options. Since the device is capable of being programmed by either the manufacturer o

39、r the user to result in a wide variety of configurations; two processing options are provided for selection in the contract. 3.6.1 Unprogrammed device delivered to the user. All testing shall be verified through group A testing as defined in 3.2.3.1 and table IIA. It is recommended that users perfor

40、m subgroups 7 and 9 after programming to verify the specific program configuration. 3.6.2 Manufacturer programmed device delivered to the user. All testing requirements and quality assurance provisions herein, including the requirements of the altered item drawing, shall be satisfied by the manufact

41、urer prior to delivery. 3.7 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the

42、 “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.7.1 Certification/compliance mark. Th

43、e certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.8 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be requir

44、ed from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certi

45、ficate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A

46、 and herein. 3.9 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.10 Notification of change for device clas

47、s M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.11 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity r

48、etain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.12 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 42 (see MIL-PRF-38535, appendix A). 3.13 Data retention. A data retention stress test shall be completed as par