DLA SMD-5962-89946 REV B-2012 MICROCIRCUIT DIGITAL HIGH SPEED CMOS 4-BIT SYNCHRONOUS DECADE UP DOWN COUNTER MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add notes to figure 4, switching waveforms and test circuit. Update the boilerplate to current requirements as specified in MIL-PRF-38535. Editorial changes throughout. jak 06-04-27 Thomas M. Hess B Update boilerplate paragraphs to the current MI

2、L-PRF-38535 requirements. - LTG 12-05-17 Thomas M. Hess REV SHEET REV SHEET REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Marcia B. Kelleher DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD M

3、ICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY Thomas J. Ricciuti APPROVED BY Michael A. Frye MICROCIRCUIT, DIGITAL, HIGH SPEED CMOS, 4-BIT SYNCHRONOUS DECADE UP/DOWN COUNTER, MONOLITHIC SILICON DRAWING APPROVAL

4、DATE 90-08-10 REVISION LEVEL B SIZE A CAGE CODE 67268 5962-89946 SHEET 1 OF 14 DSCC FORM 2233 APR 97 5962-E301-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89946 DLA LAND AND MARITIME COLUMBUS, OHIO 432

5、18-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the

6、 following example: 5962-89946 01 E A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54HC190 4-bit synchronous decade up/down cou

7、nter 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line 2 CQCC1-N20 20 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in M

8、IL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VCC) . -0.5 V dc to +7.0 V dc DC input voltage range (VIN) . -0.5 V dc to VCC + 0.5 V dc DC output voltage range (VOUT) -0.5 V dc to VCC+ 0.5 V dc DC input diode current (IIK) . 20 mA DC output diode current (per

9、pin) (IOK) 20 mA DC output current (per pin) (IOUT) 25 mA DC VCCor GND current (ICC, IGND) 50 mA Storage temperature range (TSTG) -65C to +150C Maximum power dissipation (PD) 500 mW 4/ Lead temperature (soldering, 10 seconds) . +260C Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Junctio

10、n temperature (TJ) . +175C 1.4 Recommended operating conditions. Supply voltage range (VCC) . +2.0 V dc to +6.0 V dc Input voltage range (VIN) . 0.0 V to VCC Output voltage range (VOUT) 0.0 V to VCCCase operating temperature range (TC) -55C to +125C Input rise or fall time (tr, tf): TC= -55C to +125

11、C: VCC= 2.0 V 0 to 500 ns VCC= 4.5 V 0 to 500 ns VCC= 6.0 V 0 to 400 ns VCC= 6.0 V dc . 32 ns _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise specifi

12、ed, all voltages are referenced to ground. 3/ The limits for the parameters specified herein shall apply over the full specified VCCrange and case temperature range of -55C to +125C. 4/ For TA= +100C to +125C, derate linearly at 12 mW/C Provided by IHSNot for ResaleNo reproduction or networking perm

13、itted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89946 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions Continued. Minimum pulse width, CLK (tW1): TC= +25C: VCC= 2.0 V dc . 125 ns VCC= 4.5

14、V dc . 25 ns VCC= 6.0 V dc . 21 ns TC= -55C to +125C: VCC= 2.0 V dc . 190 ns VCC= 4.5 V dc . 38 ns VCC= 6.0 V dc . 32 ns Minimum pulse width, LOAD (tW2): TC= +25C: VCC= 2.0 V dc . 120 ns VCC= 4.5 V dc . 24 ns VCC= 6.0 V dc . 20 ns TC= -55C to +125C: VCC= 2.0 V dc . 180 ns VCC= 4.5 V dc . 36 ns VCC=

15、6.0 V dc . 31 ns Minimum setup time, Dn to LOAD (ts1): TC= +25C: VCC= 2.0 V dc . 150 ns VCC= 4.5 V dc . 30 ns VCC= 6.0 V dc . 25 ns TC= -55C to +125C: VCC= 2.0 V dc . 225 ns VCC= 4.5 V dc . 45 ns VCC= 6.0 V dc . 38 ns Minimum setup time, DOWN/UP to CLK (ts2): TC= +25C: VCC= 2.0 V dc . 205 ns VCC= 4.

16、5 V dc . 41 ns VCC= 6.0 V dc . 35 ns TC= -55C to +125C: VCC= 2.0 V dc . 306 ns VCC= 4.5 V dc . 61 ns VCC= 6.0 V dc . 53 ns Minimum set up time, ENABLE to CLK (ts3): TC= +25C: VCC= 2.0 V dc . 205 ns VCC= 4.5 V dc . 41 ns VCC= 6.0 V dc . 35 ns TC= -55C to +125C: VCC= 2.0 V dc . 306 ns VCC= 4.5 V dc .

17、61 ns VCC= 6.0 V dc . 53 ns Minimum recovery time, LOAD from CLK (tREC): TC= +25C: VCC= 2.0 V dc . 150 ns VCC= 4.5 V dc . 30 ns VCC= 6.0 V dc . 25 ns TC= -55C to +125C: VCC= 2.0 V dc . 225 ns VCC= 4.5 V dc . 45 ns VCC= 6.0 V dc . 38 ns Minimum hold time, Dn to LOAD (th1): TC= +25C: VCC= 2.0 V dc . 2

18、5 ns VCC= 4.5 V dc . 5 ns VCC= 6.0 V dc . 5 ns TC= -55C to +125C: VCC= 2.0 V dc . 40 ns VCC= 4.5 V dc . 8 ns VCC= 6.0 V dc . 7 ns Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89946 DLA LAND AND MARITIME CO

19、LUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions Continued. Minimum hold time, DOWN/UP to CLK (th2): TC= +25C: VCC= 2.0 V dc . 5 ns VCC= 4.5 V dc . 5 ns VCC= 6.0 V dc . 5 ns TC= -55C to +125C: VCC= 2.0 V dc . 5 ns VCC= 4.5 V dc . 5 ns VCC= 6

20、.0 V dc . 5 ns Minimum hold time, ENABLE to CLK (th3): TC= +25C: VCC= 2.0 V dc . 5 ns VCC= 4.5 V dc . 5 ns VCC= 6.0 V dc . 5 ns TC= -55C to +125C: VCC= 2.0 V dc . 5 ns VCC= 4.5 V dc . 5 ns VCC= 6.0 V dc . 5 ns Maximum operating frequency (fMAX): TC= +25C: VCC= 2.0 V dc . 4.2 MHz VCC= 4.5 V dc . 21 M

21、Hz VCC= 6.0 V dc . 24 MHz TC= -55C to +125C: VCC= 2.0 V dc . 2.8 MHz VCC= 4.5 V dc . 14 MHz VCC= 6.0 V dc . 16 MHz 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified

22、 herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Mi

23、crocircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quick

24、search/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents ci

25、ted in the solicitation or contract. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC Standard No. 7 - Standard for Description of 54/74HCXXXXX and 54/74HCTXXXXX Advanced High-Speed CMOS Devices. (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State T

26、echnology Association, 3103 North 10thStreet, Suite 240-S Arlington, VA 22201). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89946 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 D

27、SCC FORM 2234 APR 97 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obt

28、ained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and quali

29、fied manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Qualit

30、y Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to ide

31、ntify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein. 3.2.2 Termi

32、nal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Counting sequence diagram. The counting sequence diagram shall be as spec

33、ified on figure 4. 3.2.6 Test circuit and switching waveforms. The test circuit and switching waveforms shall be as specified on figure 5. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall a

34、pply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appen

35、dix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1

36、Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow opti

37、on is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved so

38、urce of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered

39、 to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the m

40、anufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89946 DLA LAN

41、D AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Test conditions 1/ -55C TC +125C unless otherwise specified VCCGroup A subgroups Limits Unit Min Max High level output voltage VOHVIN= VIHminimum or VI

42、Lmaximum IOH= -20 A 2.0 V 1, 2, 3 1.9 V 4.5 V 4.4 6.0 V 5.9 VIN= VIHminimum or VILmaximum IOH= -4.0 mA 4.5 V 3.7 VIN= VIHminimum or VILmaximum IOH= -5.2 mA 6.0 V 5.2 Low level output voltage VOLVIN= VIHminimum or VILmaximum IOL= +20 A 2.0 V 1, 2, 3 0.1 V 4.5 V 0.1 6.0 V 0.1 VIN= VIHminimum or VILmax

43、imum IOL= +4.0 mA 4.5 V 0.4 VIN= VIHminimum or VILmaximum IOL= +5.2 mA 6.0 V 0.4 High level input voltage VIH2/ 2.0 V 1, 2, 3 1.5 V 4.5 V 3.15 6.0 V 4.2 Low level input voltage VIL2/ 2.0 V 1, 2, 3 0.3 V 4.5 V 0.9 6.0 V 1.2 Quiescent supply current (standby) ICCVIN= VCCor GND IOUT= 0.0 A 6.0 V 1, 2,

44、3 160 A Input leakage current IINVIN= VCCor GND 6.0 V 1, 2, 3 1.0 A Input capacitance CINSee 4.3.1c GND 4 10 pF Functional tests See 4.3.1d 7, 8 Propagation delay time, ENABLE to RC tPLH1, tPHL13/ CL= 50 pF See figure 5 2.0 V 9 132 ns 10, 11 198 4.5 V 9 26 ns 10, 11 40 6.0 V 9 23 ns 10, 11 34 Propag

45、ation delay time, LOAD to Qn tPLH2, tPHL23/ CL= 50 pF See figure 5 2.0 V 9 264 ns 10, 11 396 4.5 V 9 53 ns 10, 11 79 6.0 V 9 45 ns 10, 11 67 Propagation delay time, Dn to Qn tPLH3, tPHL33/ CL= 50 pF See figure 5 2.0 V 9 240 ns 10, 11 360 4.5 V 9 48 ns 10, 11 72 6.0 V 9 41 ns 10, 11 61 See footnotes

46、at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89946 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteri

47、stics Continued. Test Symbol Test conditions 1/ -55C TC +125C unless otherwise specified VCCGroup A subgroups Limits Unit Min Max Propagation delay time, CLK to Qn tPLH4, tPHL43/ CL= 50 pF See figure 5 2.0 V 9 215 ns 10, 11 325 4.5 V 9 43 ns 10, 11 65 6.0 V 9 37 ns 10, 11 55 Propagation delay time,

48、CLK to RC tPLH5, tPHL53/ CL= 50 pF See figure 5 2.0 V 9 125 ns 10, 11 190 4.5 V 9 25 ns 10, 11 38 6.0 V 9 21 ns 10, 11 32 Propagation delay time, DOWN/UP toRC tPLH6, tPHL63/ CL= 50 pF See figure 5 2.0 V 9 228 ns 10, 11 342 4.5 V 9 46 ns 10, 11 68 6.0 V 9 38 ns 10, 11 59 Propagation delay time, CLK to MAX/MIN tPLH7, tPHL73/ CL= 50 pF See figure 5 2.0 V 9 255 ns 10, 11 385 4.5 V 9 51 ns 10, 11 77 6.0 V 9 43 ns 10, 11 65 Propagation delay time, DOWN/ UP to MAX/MIN tPLH8, tPHL83/ CL= 50 pF See figure 5 2.0 V 9 190 ns 10, 11 285 4.5 V 9 38 ns 10, 11 57 6.