DLA SMD-5962-89505 REV A-2005 MICROCIRCUIT DIGITAL CMOS MEMORY MANAGEMENT BLOCK PROTECTION UNIT MONOLITHIC SILICON《硅单片内存管理数据块保护部件互补型金属氧化物半导体数字微电路》.pdf

《DLA SMD-5962-89505 REV A-2005 MICROCIRCUIT DIGITAL CMOS MEMORY MANAGEMENT BLOCK PROTECTION UNIT MONOLITHIC SILICON《硅单片内存管理数据块保护部件互补型金属氧化物半导体数字微电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-89505 REV A-2005 MICROCIRCUIT DIGITAL CMOS MEMORY MANAGEMENT BLOCK PROTECTION UNIT MONOLITHIC SILICON《硅单片内存管理数据块保护部件互补型金属氧化物半导体数字微电路》.pdf（27页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update boilerplate to MIL-PRF-38535 requirements. - CFS 05-12-08 Thomas M. Hess REV SHET REV A A A A A A A A A A A A SHEET 15 16 17 18 19 20 21 22 23 24 25 26 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 1

2、3 14 PMIC N/A PREPARED Wanda L. Meadows DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Thomas M. Hess COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Monica L. Poelking MICROCIRCUIT, DIGITAL, CMOS, MEMORY MANA

3、GEMENT BLOCK PROTECTION UNIT, AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 92-03-19 MONOLITHIC SILICON AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-89505 SHEET 1 OF 26 DSCC FORM 2233 APR 97 5962-E012-06 Provided by IHSNot for ResaleNo reproduction or networking permitted

4、without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89505 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microci

5、rcuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89505 01 X X Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify t

6、he circuit function as follows: Device type Generic number Circuit function Clock speed 01 P1753 MMU/COMBO with bus arbitration 20 MHz 02 P1753 MMU/COMBO with bus arbitration 30 MHz 03 P1753 MMU/COMBO with bus arbitration 40 MHz 04 P1753 MMU/COMBO 20 MHz 05 P1753 MMU/COMBO 30 MHz 06 P1753 MMU/COMBO

7、40 MHz 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style T See figure 1 64 Dual-in-line with gull-wing leads U See figure 1 68 Leaded chip carrier X See figure 1 64 Dual-in-line Y See figure 1 68

8、 Leaded chip carrier with gull-wing leads Z See figure 1 68 Pin grid array 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ Supply voltage range, (VCC) -0.5 V dc to +7.0 V dc Input voltage range . -0.5 V dc to VCC+ 0.5 V dc Storage tem

9、perature range . -65C to +150C Input current range -30 mA to +5 mA Current applied to any output 2/ . 150 mA Maximum power dissipation (PD) 3/ 1.5 W Lead temperature range (soldering, 10 seconds) +300C Thermal resistance, junction-to-case (JC): Cases X and T. 8C/W Cases Y and U 5C/W Case Z. 6C/W _ 1

10、/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Duration of 1 second or less. 3/ Must withstand the added PDdue to short circuit test; e.g., IOS. Provided by IHSNot for

11、ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89505 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Supply voltage range. 4.5 V dc to 5

12、.5 V dc Case operating temperature range (TC) -55C to +125C Operating power dissipation (PD) (outputs open): Device types 01 and 04 . 0.20 W maximum Device types 02 and 05 . 0.30 W maximum Device types 03 and 06 . 0.40 W maximum 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and ha

13、ndbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuit

14、s, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1750 - Sixteen-Bit Computer Instruction Set Architecture MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HD

15、BK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Phi

16、ladelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has be

17、en obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and

18、 qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the

19、Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required

20、to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Terminal connections. The terminal connections shall be as specified on figure 1. 3.

21、2.2 Case outlines. The case outlines shall be in accordance with 1.2.2 herein and as specified on figure 2. 3.2.3 Functional block diagram. The functional block diagram shall be as specified on figure 3. 3.2.4 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as

22、 specified on figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89505 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 3.3 Electrical performance

23、 characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II.

24、 The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SM

25、D PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance ind

26、icator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in

27、 MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certifica

28、te of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs ag

29、ent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license fro

30、m IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89505 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified 1/ Group

31、A subgroups Device type Limits Unit Min Max Input high voltage VIH1, 2, 3 All 2.0 VCC+ 0.5 V Input low voltage VIL2/ 1, 2, 3 All -0.5 0.8 V Input clamp diode voltage VCDVCC= 4.5 V, IIN= -18 mA 1, 2, 3 All -1.2 V IOH= -2.0 mA 2.4 Output high voltage VOHVCC= 4.5 V, VIN= 2.0 V, 0.8 V IOH= -300 A 1, 2,

32、3 All VCC 0.2 V IOL= 8.0 mA 0.5 Output low voltage, except EXT ADR0 EXT ADR7VOLVCC= 4.5 V, VIN= 2.0 V, 0.8 V IOL= 300 A 1, 2, 3 All 0.2 V IOL= 20 mA 0.5 Output low voltage, EXT ADR0 EXT ADR7VOLVCC= 4.5 V, VIN= 2.0 V, 0.8 V IOL= 300 A 1, 2, 3 All 0.2 V Input high current, except IB0 IB15, EDC0 EDC5,

33、EXT ADR0- EXT ADR7IIH1, 2, 3 All 10 A Input high current, IBO IB15, EDC0 EDC5, EXT ADR0- EXT ADR7IIHVIN= VCCVCC= 5.5 V 1, 2, 3 All 50 A Input low current, except IB0 IB15, EDC0 EDC5, EXT ADR0- EXT ADR7IIL1, 2, 3 All -10 A Input low current, IB0 IB15, EDC0 EDC5, EXT ADR0- EXT ADR7IILVIN= GND VCC= 5.5

34、 V 1, 2, 3 All -50 A Output three-state current IOZHVOUT= 2.4 V VCC= 5.5 V 1, 2, 3 All 50 A Output three-state current IOZLVOUT= 0.5 V VCC= 5.5 V 1, 2, 3 All -50 A See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDAR

35、D MICROCIRCUIT DRAWING SIZE A 5962-89505 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified 1/ Group A sub

36、groupsDevice type Limits Unit Min Max Quiescent power supply current (CMOS input levels, active) ICCQCVIN 0.2 V or VCC -0.2 V, f = 0 MHz, outputs open, VCC= 5.5 V 1, 2, 3 All 60 mA Quiescent power supply current (TTL input levels, active) ICCQTVIN= 3.4 V, f = 0 MHz, all inputs, outputs open, VCC= 5.

37、5 V 1, 2, 3 All 110 mA f = 20 MHz 01, 04 40 f = 30 MHz 02, 05 50 Dynamic power supply current ICCDVIN= 0 V to VCC,tr= tf= 2.5 ns, outputs open, VCC= 5.5 V f = 40 MHz 1, 2, 3 03, 06 60 mA Output short circuit current IOS3/ VOUT= GND VCC= 5.5 V 1, 2, 3 All -25 mA Input capacitance CIN2/ See 4.3.1c, in

38、puts only 4 All 10 pF Output/bi-directional capacitance COUTSee 4.3.1c, outputs, (including I/O buffers) 4 All 15 pF Functional tests See 4.3.1d, VCC= 4.5 V, 5.5 V 7, 8 All 01, 04 25 02, 05 23 MMU cache hit TD/I(EXT ADR)V9, 10, 11 03, 06 23 ns 01, 04 25 02, 05 20 External address error TSTRBD (EXT A

39、DR ERR)L9, 10, 11 03, 06 16 ns 01, 04 25 02, 05 20 Error correction read cycle TC(IBD CORR) 9, 10, 11 03, 06 19 ns 01, 04 35 02, 05 30 Error correction read cycle TIBDV(SING ERR)H9, 10, 11 03, 06 25 ns 01, 04 25 02, 05 20 Error correction read cycle TC (SING ERR)L9, 10, 11 03, 06 12 ns 01, 04 30 02,

40、 05 25 EDAC or parity write cycle TIBDV(EDC GEN)VSee figure 4 VCC= 4.5 V 9, 10, 11 03, 06 23 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89505 DEFENSE SUPPLY CENTER COLUM

41、BUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified 1/ Group A subgroups Device type Limits Unit Min Max 01, 04 25 02, 05 20 MMU cache

42、 miss TSTRBA (EX RDY)L9, 10, 11 03, 06 12 ns 01, 04 25 02, 05 20 MMU cache miss TC (EX RDY)H9, 10, 11 03, 06 12 ns 01, 04 25 02, 05 22 MMU cache miss TC (WR PROT)L9, 10, 11 03, 06 18 ns 01, 04 25 02, 05 20 MMU cache miss TSTRBDH(WR PROT)H9, 10, 11 03, 06 16 ns 01 35 02 25 Arbiter low to high priorit

43、y TC(GNT1)H9, 10, 11 03 18 ns 01 35 02 25 Arbiter low to high priority TC(GNT0)L9, 10, 11 03 18 ns 01 35 02 25 Arbiter high to low priority TC(GNT0)H9, 10, 11 03 18 ns 01 35 02 25 Arbiter high to low priority TC(GNT1)L9, 10, 11 03 18 ns 01, 04 30 02, 05 25 Address ready TC(RDYA) 9, 10, 11 03, 06 17

44、ns 01, 04 30 02, 05 28 Clock to IB out valid (I/O Read) TFC (IB OUT)V9, 10, 11 03, 06 25 ns 01, 04 34 02, 05 30 Parity mode TIBDIN(MEM PAR ERR) 9, 10, 11 03, 06 25 ns 01, 04 50 02, 05 45 Memory protect error TC (MEM PRT ERR) See figure 4 VCC= 4.5 V 4/ 9, 10, 11 03, 06 40 ns See footnotes at end of t

45、able. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89505 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characterist

46、ics - Continued. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified 1/ Group A subgroups Device type Limits Unit Min Max 01, 04 25 02, 05 20 Write protect cache hit TSTRBD (WR PROT) 9, 10, 11 03, 06 16 ns 01, 04 25 02, 05 22 Write protect cache miss TC (WR PROT)L9, 10, 1

47、1 03, 06 18 ns 01, 04 25 02, 05 22 Write protect cache miss TSTRBDH(WR PROT)H9, 10, 11 03, 06 18 ns 01, 04 50 02, 05 45 Cache hit (BPU protection error) TD/I (PROT FLAG) 9, 10, 11 03, 06 40 ns 01, 04 40 02, 05 35 Cache hit (MMU key-lock error) TD/I (PROT FLAG) 9, 10, 11 03, 06 30 ns 01, 04 45 02, 05

48、 35 Cache miss (BPU protection error) TC (PROT FLAG) 9, 10, 11 03, 06 30 ns 01, 04 25 02, 05 20 Cache miss (MMU key-lock error) TC (PROT FLAG) 9, 10, 11 03, 06 20 ns 01, 04 32 02, 05 30 Clock to EXT ADR valid (miss) TC (EXT ADR) See figure 4 VCC= 4.5 V 4/ 9, 10, 11 03, 06 23 ns 1/ Unless otherwise specified, testing shall be conducted at worst-case conditions. 2/ VIL= -3.0 V for pulse widths less than or equal to 20 ns. 3/ Duration of the short should not exceed one second; only one output may be shorted at a time. 4/ Pulse width of WR PROT/PROT FL