DLA SMD-5962-89449 REV A-1994 MICROCIRCUITS DIGITAL HIGH PERFORMANCE CHMOS III NUMERIC PROCESSOR EXTENSION MONOLITHIC SILICON《硅单片数字处理器扩建工程高性能CHMOS III数字微电路》.pdf

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1、SMD-5962-87449 REV A m 9999996 0070990 382 DEscRIpIToN Add device type 03. -te boiler plate. atoria1 changes thi-aughau t. LTR (YR-WO-DA) 94 -12 -1 6 A SIZE CAGE CODE A 67268 5962-89449 PMTC N/A STANDAFtD MICROCIRCUIT DRAWING THIS DRAUINC IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE D

2、EPARTMENT OF DEFENSE AMSC N/A )ESC FORM 193 JUL 94 PREPARED BY Vanda L. Meadows CHECKED BY Thomas M. Hess Sr APPROVED ar Tim H. Noh DRAUING APPROVAL DATE 92-06-16 REVISICM LEVEL A M. L. pOelkh3 DEFENSE ELEcTw3NICS SUPPLY CENITR mm, OHIO 45444 SHEET 1 OF 18 - 5962-E426-94 DISTRIBUTION STATEMENT A. Ap

3、proved far public release; distribution is unlimited. - Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-87449 REV A I I STANDARD SIZE 5962-89449 MICROCIRCUIT DRAWING A DAYTON, OHIO 45444 REs7ISIONLEvEL SHEET DEFENSE ELECTRONICS SUPPLY CENTER

4、 A 2 rn 99b 0070993 219 rn I 1. SCOPE 1.1 Scope. This drawing describes device requirmts for class 6 microcircuits in accordance uith 1.2.1 of MIL-STD-883, IIProvisions for the use of MIL-STD-883 in conjunction uith compliant non-JAN devicesL1. 1.2 Part or Identifying Nhr (PIN). lhe corrplete PIN sh

5、all be as shown in the following example: I 5 962 - 89449 O1 P X I I I I I I I I I I I I I I I I Drawing nuiiber (1.2.1 1 (1.2.2) (1.2.3) 1.2.1 Device tvpe(s2. The device type(s) shall identify the circuit function as follous: Device tme Generic nunber Circuit function Frequency o1 80C187- 1 O 02 80

6、C 187- 12 03 8OC187-16 80-bi t nuneric processor extension 80-bit nuneric processor extension 80-bit nuneric processor extension 10 MHr 12 MHr 16 MHz 1.2.2 Case outline(s). lhe case outline(s) shall be as designated in MIL-STD-1835, and as folious: Outline letter Descriptive designator Termi na 1 s

7、Packaqe style P X GDIPI-T40 or CDIP2-T40 See figure 1 40 Dual-in-line package 68 Ceramic quad flat package 1.2.3 Lead finish. lhe lead finish shalt be as specified in MIL-STO-883 (see 3.1 herein). Finish letter shall not be marked on the microcircuit or its packaging. finishes A, 6, and C are consid

8、ered acceptable and interchangeable uithout preference. The 11x11 designation is for use in specifications when lead 1.3 Absolute maxinm ratinqs. Storage tenperature range - - - - - - - - - - - - - - - - - - - - - - - - - - - - -65C to +150“C -0.5 V to Vcc + 0.5 V Voltage on any pin (respect to grou

9、nd) - - - - - - - - - - - - - - - - - - - - - Leed tenperature (soldering 90 seconds) - - - - - - - - - - - - - - - - - - - - - Thermal resistance, junction-to-case (6 1: Maxim power dissipation (p ) - - - - - - - - - - - - - - - - - - - - - - - - EO mw +275 Oc CaseQ-JC-_-_-_- - - See MIL-STD-1835 c

10、asex-.- 8.5 “C/U Junction tenperature (TJ) - - - - - - - - - - - - - - - - - - - - - - - - - - - - +150“C 1.4 Recamnended operating conditions. -55Oc to +125“C 4.75 V dc to 5.25 V dc Case operating tenperature range - - - - - - - - - - - - - - - - - - - - - - - - Supply voltage (V )- - - - - - - - -

11、 - - - - - - - - - - - . - - - - - - * Frequency of oper%i on: Device type 01 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10 MHz Devicetype02- 12.5 MHz Device type 03 - - - - - - - - - - - - - - - - - - - - - - - - - - - 16 MHz 2. APPLICABLE OOCUMENTC 2.1 Goverrunent specification. sta

12、ndard, and bulletin. Unless otherwise specified, the following specification, standard, and bulletin of the issue listed in that issue of the Department of Defense Index of Specifications and Standards specified in the solicitation, form a part of this drawing to the extent specified herein. SPECIFI

13、CAlIN Mi LI TARY MIL-1-38535 - Intergrated Circuits (Microcircuits) Manufacturing, Genere( Specification for. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-87449 REV A 9997996 0070992 155 STANDARD SIZE MICROCIRCUIT DRAWING A DAYTON, OHIO 4

14、5444 DEFENSE ELECTRONICS SUPPLY CENTER STANDARD 5962-89449 ms1ONLEvEL SHEFT A 3 MI L I 7 ARY MIL-STO-883 - Test Methods and Procedures for Microelectronics. MIL-STD-1835 - Microcircuit Case Outlines. BULLETIN MIL I TARY MIL-BUL-103 - List of Standardized Military Drawings (SMD1s). (Copies of the spe

15、cification, standard, and bulletin required by manufacturers in connection uith specific acquisition functions should be obtained from the contracting activity or as directed by the contracting activity.) 2.2 Order of precedence. In the event of a conflict between the text of this drauing and the re

16、ferences cited herein, the text of this drauing shall take precedence. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with 1.2.1 of MIL-STD-883, “Provisions for the use of MIL-STD-883 in conjunction uith campliant non-JAN devices“ and as specified here

17、in. Product built to this drauing that is produced by a Qualified Masnufacturer Listing (QML) certified and qualified manufacturer or a manufacturer uho has been granted transitional certification to MIL-1-38535 may be processed as QML product in accordance uith the manufacturers approved program pl

18、an and qualifying activity approval in accordance uith MIL-1-38535. requirements herein. These modifications shall not effect form, fit, or function of the device. shall not affect the PIN as described herein. required to idenify when the QML flou option is used. 3.2 Desian, construction, and Dhysic

19、al dimensions. specified in MIL-STD-883 (see 3.1 herein) and herein. Case outtinets). This ML flou as docunented in the Quality Management (W) plan may make nodifications to the These modifications A Wi or tlQMLI1 certification mark in accordance uith MIL-1-38535 is The design, construction, and phy

20、sical dimensions shall be as 3.2.1 3.2.2 Terminal connections. lhe terminal comections shall be as specified on figure 2. 3.2.3 Block diasrarn. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance The case outline(s1 shall be in accordance with 1.

21、2.2 herein, and figure 1. The block diagram shall be as specified on figure 3. characteristics are as specified in table 1 and shall apply over the full case operating temperature range. 3.4 Electrical test reauirements. The electrical test requirements shall be the subgroups specified in table il.

22、lhe electrical tests for each subgroup are described in table 1. 3.5 Marking. Marking shall be in accordance with MIL-STD-883 (see 3.1 herein). The part shall be marked uith the PIN listed in 1.2 herein. herein). In addition, the manufacturers PIN may also be marked as listed in MIL-BUL-103 (see 6.6

23、 3.6 Certificate of condiance. A certificate of canpliance shall be required from a manufacturer in order to be The certificate of compliance subnitted to listed as an approved source of supply in MIL-BUL-103 (see 6.6 herein). DESC-EC prior to listing as an approved source of supply shall affirm tha

24、t the manufacturers product meets the requirements of MIL-STD-883 (see 3.1 herein) and the requirements herein. provided with each lot of microcircuits delivered to this drawing. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-STD-883 (see 3.1 herein) shall be 3.8 Not

25、ification of chanse. Notification of change to DESC-ECC shall be required in accordance with MIL-STO-883 (see 3.1 herein). 3.9 Verification and review. DESC, DESCNs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required docunentation. at the

26、option of the revieuer. Offshore docunentation shall be made available onshore Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-TABLE i. Electrical performance characteristics. ;roup A ;ubgroups 1,2,3 1,2,3 Conditions 1/ Form -55C 5 Tc S +125C 4.75 V

27、S VCc S 5.25 V unless otherwise specified Device Limits Unit type Min Hax All -0.5 2/ +0.8 V All -0.5 2/ +0.8 V L CL 1,2,3 All 2.2 vcc+.5 z/ IVIH I v 1,2,3 o v v vcc, (ILI I v, = 5fY5 v All 2.2 vcc+.5 2/ v 0.45 V V Vcc-0.45 V, )ILo I Vcc = 5.25q Va VoH Vcc = 5.25 V Icc loL = 3.0 IM, Vcc = 4.75 V IOH

28、 = -800 M, Vcc 4.75 V 1,2,3 ICo 1 FC = 1 MHr, see 4.3.1 l Alt -10 +10 when strapped to V (LowI, %e CLK input is divided by two to produce the internat clock signal. auring the RESET sequence, this input mist be stable at least four internal clock cycles before RESET goes low. An active high input uh

29、ich, when active, causes the device to terminate its present activity and enter a dormant state. least four internal clock cycles in order to take effect. internally active for 25 clock cycles after termination of RESET, the first instruc- tion should not be written to the device until 25 internal c

30、locks after the falling edge of RESET. It is capable of when strapped to V (high), CKII allows This input must remain active (high) for at Since the device is An active low output which indicates that an unmasked exception has occurred. ERROR can change state only when BUSY is active. PEREQ BUSY An

31、active high output which signals to the CPU that the device is ready for data transfer to/from its FIFO stack. PEREP is deactivated after the first three transfers, and subsequently after every four transfers. This signal always goes inactive before BUSY goes inactive. An active high output which si

32、gnals to the CPU that the device is currently executing an instruction. When there are more than five data transfers, During the RESET sequence this pin is active (high). Active high inputs which, along uith the select signals % and NPSZ, allow the CPU to direct the operation of the device. D15 - Do

33、 - NPRD - NPUR _c NPSl, NPSZ System power inputs; capacitors should be USYgtueen Vcc and Vss. System ground inputs; all Vs pins should be tied together, and local decoupling capacitors should be used beSueen Vcc and Vss. pins should be tied together, and local decoupling vcc “SS Bidirectional pins u

34、sed to transfer data and opcodes between the CPU and the device. Other buffers/drivers driving the local data bus must be disabled when the CPU reads from the device. Do is the least significant data bit. An active Lou input which enabhtransfers of data from the device to the CPU. This input is vali

35、d only when NPSl and NPS2 are both active. An active lou input which enabktransfers of data from the CPU to the device. This input is valid only when NPSl and NPSZ are both active. Active low and active high (respectively) select signals; concurrent assertion of these signals indicates that the CW i

36、s performing an escape instruction and enables the device to execute that instruction. No data transfer involving the device occurs unless the device is selected by these lines. They are normally connected directly to the corresponding CW data pins. STANDARD SIZE MICROCIRCUIT DRAWING A DAYTON, OHIO

37、45444 REVISIONLEVEL DEFENSE ELECTRONICS SUPPLY CENTER A 5962-89449 SHEET 18 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT RAUING SWRCE APPROVAL BULLETIN DATE: 94-12-16 Approved sources of supply for SMD 5962-89449 are listed b

38、elow for inmediate acquisition only and shall be added to MIL-BUL-103 during the next revision. The vendors listed below have agreed to this drawing and a certificate of compliance has been suhnitted to and accepted by DESC-EC. This bulletin is superseded by the next dated revision of MIL-BUL-103. M

39、IL-BUL-103 uill be revised to include the addition or deletion of sources. 5962-8944901W 5962-8944901XX 5962-8944902X 5962-8944902XX 5962-8944903QX 5962-8944903XX Standard microcircuit drauing PiN 34649 nD80C187-10/B 34649 M80C187-10/B 34649 MD80C187- 12/B 34649 MQ80C187-12/6 34649 MD8OC187- 16/B 34

40、649 MP80C187-16/B Vendor nunber I CAGE 1 Vendor sirni lar PIN I/ - 1/ Caution. Do not use this nurber for item acquisition. may not satisfy the performance requirements of this drauing. Items acquired to this nunber Vendor CAGE &er 34649 Vendor name and address Intel Corporation Robert Noyce Bldg. K

41、O01 2200 Mission College Blvd P O Box 58119 Santa Clara, CA 95052-8119 Point of contact: 5000 West Chandler Boulevard Chandler A2 85226 The information contained herein is disseminated for convenience only and the Covermnt assms no liability whatsoever for any inaccuracies in this information bulletin. I I Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-